Thin-Film Transistor Array Layout for Short-Channel High-Resolution Panels
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Solution Overview
Problem
Existing thin-film transistor array substrates face challenges in achieving high integration, short channel lengths, and high resolution while maintaining transistor performance and protecting against electrical circuit discontinuities.
Innovation Solution
A thin-film transistor array substrate design with specific transistor structures, including overlapping electrodes and active layers, and a storage capacitor configuration to enhance integration, operating margin, and reduce device area, while protecting against electrical breaks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistor size is reduced to achieve high integration and high resolution, then device area is reduced, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent employs a dual-gate transistor structure where the gate electrode extends in two dimensions (length and width) to control the channel, rather than a conventional single-gate structure. This dual-dimensional gate control allows for better electrostatic management in scaled devices, improving manufacturing precision and reliability while maintaining reduced device area for high resolution displays.
Solution Approach 2:
The transistor is segmented into multiple functional regions including first and second gate electrodes, source/drain regions, and channel regions. This segmentation allows independent optimization of each region's dimensions and properties, enabling precise control over transistor characteristics even at reduced sizes, thereby maintaining manufacturing precision while achieving high integration.
2Length of moving object
If transistor size is reduced to achieve short channel length, then integration density increases, but transistor performance may be degraded
Solution Approach 1:
The dual-gate structure provides control from two directions (top and bottom gates), effectively doubling the gate control influence on the short channel. This compensates for the reduced channel length by enhancing the electric field control, maintaining transistor performance and reliability even with shortened channels for higher integration density.
Solution Approach 2:
The patent adjusts multiple parameters including gate electrode widths, channel thickness, and doping concentrations to optimize transistor performance in short channel configurations. By carefully tuning these parameters, the transistor maintains reliable operation despite the reduced channel length, achieving both high integration and sustained performance.
3Ease of manufacture
If ease of processing is pursued in panel fabrication, then manufacturing complexity is reduced, but transistor performance is degraded
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming the first gate electrode and its insulating layer, depositing the semiconductor layer, forming the second gate electrode, and creating source/drain regions. Each stage uses standardized processing techniques that are easier to manufacture, while the cumulative effect of these segmented steps achieves the complex dual-gate structure with high transistor performance.
Solution Approach 2:
The gate insulating layer serves multiple functions: as an insulator between the first gate electrode and semiconductor layer, as a dielectric for the first capacitor, and as part of the overall gate control structure. This multi-functionality reduces the number of separate components and processing steps, easing manufacturing while maintaining transistor performance.
Data Source
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AI summary
An electronic device can include a panel; a driver circuit configured to drive the panel; and first and second transistors disposed in the panel, the first and second transistors including: a first electrode of the first transistor, the first electrode being disposed on a substrate; a first insulating film disposed on the substrate, overlapping an edge of the first electrode and having an open area for receiving portions of the second transistor; a second electrode of the first transistor, the second electrode being disposed on the first insulating film and overlapping with a portion of the first electrode; third and fourth electrodes of the second transistor, the third electrode and the fourth electrode being disposed on a same layer as the second electrode and spaced apart from the second electrode, the open area of the first insulating film being disposed between the third electrode and the fourth electrode; a first active layer of the first transistor, the first active layer being disposed on the first electrode, the first insulating film and the second electrode; and a second active layer of the second transistor, the second active layer being disposed on the third and fourth electrodes and across the open area of the first insulating film.