TFT Array Substrate 2-Mask Photolithography
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Solution Overview
Problem
The manufacturing of thin film transistor array substrates for liquid crystal displays requires a significant number of mask processes, leading to high costs, and further reduction is necessary to achieve a 2-mask process for cost optimization.
Innovation Solution
A method involving sequential deposition of conductive materials and gate insulating layers, followed by resist pattern formation and etching processes, utilizing a 2-mask photolithography process or an imprinting process to simplify the manufacturing steps and reduce the number of mask processes, allowing for the formation of gate lines, data lines, source and drain electrodes, and pixel electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask processes are used to manufacture thin film transistor array substrate, then the manufacturing precision and structural integrity are improved, but the manufacturing cost increases and the number of process steps increases
Solution Approach 1:
The patent combines multiple mask processes into a single mask process by integrating the formation of gate lines, data lines, source/drain electrodes, and pixel electrodes into one photolithography step. This merging approach reduces the number of mask processes from multiple steps to just one, thereby lowering manufacturing cost and simplifying the production process while maintaining the required structural integrity of the thin film transistor array substrate
Solution Approach 2:
The single mask process developed in the patent serves multiple functions simultaneously: it defines the patterns for gate lines, data lines, source/drain electrodes, and pixel electrodes all in one step. This multi-functional mask process eliminates the need for separate mask processes for each component, achieving cost reduction without compromising the precision required for each individual structure
2Manufacturing precision
If multiple mask processes are used to manufacture thin film transistor array substrate, then the manufacturing precision is improved, but the productivity decreases due to increased process time
Solution Approach 1:
The patent merges multiple sequential mask processes into a single integrated photolithography process. By combining the patterning of gate lines, data lines, source/drain electrodes, and pixel electrodes into one mask step, the total process time is significantly reduced, thereby improving productivity and production efficiency while maintaining the necessary pattern accuracy through optimized single-step photolithography parameters
3Ease of manufacture
If the number of mask processes is reduced to two or less, then the manufacturing cost is reduced, but the manufacturing precision may be compromised
Solution Approach 1:
The patent applies local quality by designing the single mask process with spatially varying exposure conditions and resist development parameters tailored to different regions of the substrate. This allows the single mask process to achieve the precise pattern definition normally requiring multiple steps, maintaining high manufacturing precision while reducing the number of mask processes to two or less for cost efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the number of mask processes to two, thereby lowering the manufacturing cost and simplifying the production of thin film transistor array substrates while maintaining the necessary structural integrity and functionality for liquid crystal displays.
Implementation Method 1
sequentially depositing a first conductive material, a gate insulating layer, a semiconductor layer, and a second conductive material on a substrate
Implementation Method 2
forming a first resist pattern having three height levels on the second conductive material; forming a gate line, a data line that crosses the gate line and has first and second slit units, a source electrode connected to the data line and having a third slit unit, and a drain electrode positioned opposite the source electrode with a channel interposed between the source electrode and the drain electrode and having a fourth slit unit, through a plurality of etching processes using the first resist pattern
Implementation Method 3
removing the second resist pattern and the third conductive material deposited on the remaining passivation layer through a lift-off process to pattern a pixel electrode
Data Source
AI summary
Disclosed is a method of manufacturing a TFT array substrate having a reduced number of mask processes. The method includes sequentially depositing a first conductive material, a gate insulating layer, a semiconductor layer, and a second conductive material on a substrate, and forming a first resist pattern having three height levels on the second conductive material. The method further includes forming a gate line, a data line that crosses the gate line and has first and second slit units, a source electrode connected to the data line and having a third slit unit, and a drain electrode positioned opposite the source electrode with a channel interposed between the source electrode and the drain electrode and having a fourth slit unit, through a plurality of etching processes using the first resist pattern.