TFT Array Substrate Backup Common Electrode Prevents Short Circuits
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Solution Overview
Problem
Conventional TFT array substrates face issues with short circuits between the pixel electrode and the common electrode line due to manufacturing errors during the etching process, which can lead to bright spots or lines on the liquid crystal display panel, primarily because the passivation and gate insulating layers are prone to fracture and erosion.
Innovation Solution
Incorporating a backup common electrode line positioned between the gate insulating layer and the passivation layer, electrically insulated from the data line, which is designed to prevent damage from etching errors and fractures, thereby avoiding short circuits between the pixel electrode and the common electrode line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the passivation layer and gate insulating layer are made of the same or similar material to simplify manufacturing, then the manufacturing process is easier, but the layers become prone to fracture and erosion during etching, causing short circuits
Solution Approach 1:
The patent divides the common electrode structure into two separate conductive layers: a first common electrode in the gate insulating layer and a second common electrode in the passivation layer. This segmentation allows each layer to be independently designed with different materials and etching resistances, preventing the propagation of manufacturing defects while maintaining ease of manufacture through standardized layer-by-layer fabrication processes.
Solution Approach 2:
The patent introduces a buffer structure (the first common electrode) between the gate insulating layer and the second common electrode in the passivation layer. This buffer provides beforehand cushioning by absorbing etching errors and material fractures before they can propagate to cause short circuits, thereby enhancing reliability without significantly complicating the manufacturing process.
2Device complexity
If the through-hole in the passivation layer is fabricated by conventional etching process, then the manufacturing process is simpler, but manufacturing errors cause the passivation layer to fracture and the gate insulating layer to erode, leading to short circuits
Solution Approach 1:
The patent segments the common electrode into two separate conductive structures located in different layers. This segmentation isolates the etching processes, so that errors in one layer do not directly affect the other. The first common electrode serves as a reference structure that can be fabricated with conventional etching, while the second common electrode is positioned to avoid direct exposure to etching errors, thereby maintaining manufacturing precision without significantly increasing device complexity.
Solution Approach 2:
The first common electrode in the gate insulating layer acts as an intermediary structure between the substrate and the second common electrode in the passivation layer. This intermediary provides a stable reference plane and protects against the propagation of etching errors, allowing conventional etching processes to be used while maintaining manufacturing precision through the buffering effect of the intermediate layer.
3Reliability
If the common electrode line is positioned directly opposite the pixel electrode, then the electrical connection is more direct, but any fracture or erosion at this position causes short circuit between pixel electrode and common electrode line
Solution Approach 1:
The patent segments the common electrode path into two separate conductive elements: the first common electrode in the gate insulating layer and the second common electrode in the passivation layer. This segmentation creates redundant electrical pathways, so that a fracture in one layer does not necessarily cause a short circuit. The direct opposite positioning is maintained for electrical efficiency, while the segmented structure provides reliability through distributed protection against fractures and erosion.
Data Source
AI summary
A TFT array substrate, a fabrication method thereof and a display device. The TFT array substrate, comprising: gate lines (19), data lines (20) and a plurality of pixel units, each pixel unit comprises: a common electrode line (11), a gate insulating layer (16), a passivation layer (17) and a pixel electrode (12) in this order, wherein a backup common electrode line (41) is disposed at a position between the gate insulating layer (16) and the passivation layer (17) and opposite to the common electrode line (11), the backup common electrode line (41) is electrically insulated from the data line (20). The TFT array substrate with this structure can avoid the short circuit between the pixel electrode (12) and the common electrode line (11).