TFT Array Substrate Edge Alignment for Leakage Current Reduction
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Solution Overview
Problem
In liquid crystal display panels, the exposure of semiconductor layers outside the source/drain electrode metal layers leads to increased leakage current and reduced pixel voltage holding capacity due to refracted or reflected light, necessitating a new TFT array substrate and manufacturing method.
Innovation Solution
A manufacturing method for a TFT array substrate involving five masking processes, where the semiconductor layer is patterned to have edges flush with the source and drain electrodes, using dry etching to remove exposed semiconductor material and reduce photoelectric sensitivity, and forming a pixel electrode connected through a through-hole in the passivation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the semiconductor layer protrudes outside the source/drain electrode metal layer to ensure proper alignment, then the alignment between layers is improved, but the exposed semiconductor layer causes increased leakage current and reduced pixel voltage holding capacity due to light irradiation
Solution Approach 1:
The patent extracts and removes the exposed semiconductor layer tails that protrude outside the source/drain electrode metal layer through a dedicated etching process. This eliminates the harmful exposed regions that cause leakage current while maintaining the necessary alignment between layers during manufacturing.
Solution Approach 2:
The patent performs preliminary patterning of the semiconductor layer to define its boundaries before final electrode formation. By pre-establishing the semiconductor layer pattern with controlled edges, the alignment requirements are simplified and the risk of exposed tails causing leakage is prevented from the outset.
2Manufacturing precision
If five masking processes are used to form the TFT device with proper layer alignment, then the manufacturing precision is improved, but the process complexity and manufacturing time increase
Solution Approach 1:
The patent merges multiple functions into fewer masking processes. Specifically, certain masking steps are combined to achieve both alignment and pattern definition simultaneously, reducing the total number of masking processes from five to fewer steps while maintaining manufacturing precision.
Solution Approach 2:
The patent employs self-aligned processes where previously formed structures serve as their own masks for subsequent patterning steps. This self-service approach eliminates the need for separate alignment masks, reducing process complexity while ensuring precise layer alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases leakage current, improves light stability, and reduces the size of the TFT device by eliminating exposed semiconductor material, simplifying processes and saving layout space.
Implementation Method 1
when refracted or reflected light irradiates to a portion of the semiconductor layer of the TFT device which is exposed outside, it easily causes leakage current of the TFT device to increase
Data Source
AI summary
The present disclosure provides a TFT array substrate and a manufacturing method thereof. For the manufacturing method, a source electrode and a drain electrode are formed at first, and then edges of the source electrode and the drain electrode are used as masks to pattern a semiconductor layer to form an amorphous silicon island, which makes edges of the amorphous silicon island flush with the edges of the source electrode and the drain electrode, and completely removes the exposed semiconductor layer outside a metal layer, thereby decreasing photoelectric sensitivity of a TFT device, decreasing a size of the TFT device, and being beneficial for saving layouts and simplifying processes.