TFT Array Substrate Single Mask Patterning
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Solution Overview
Problem
The existing manufacturing processes for thin film transistor (TFT) array substrates require multiple masks, increasing production costs and complexity.
Innovation Solution
A method that reduces the number of masks used by forming the gate electrode, common electrode, gate insulation layer, active layer, and source/drain metal layer in one or two patterning processes, allowing for the simultaneous formation of the pixel electrode and passivation layer in a single step, thereby minimizing the number of masks required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks are used in the manufacturing process of TFT array substrate, then the manufacturing precision and pattern definition are improved, but the device complexity and production cost increase
Solution Approach 1:
The patent combines multiple patterning steps into a single mask process by forming the gate electrode, common electrode, gate insulation layer, active layer, and source/drain metal layer patterns simultaneously using one mask. This merging of multiple patterning operations into a single step directly reduces the number of masks required while maintaining the necessary manufacturing precision through careful design of the single mask pattern and corresponding deposition/etching sequence.
Solution Approach 2:
The single mask used in the invention serves multiple functions that would traditionally require separate masks: it defines patterns for the gate electrode, common electrode, gate insulation layer, active layer, and source/drain metal layer all in one operation. This multi-functional mask approach reduces device complexity by eliminating the need for multiple specialized masks while still achieving precise pattern definition for all these different structural elements.
2Device complexity
If the number of masks is reduced in the TFT array substrate manufacturing process, then the production cost and device complexity are reduced, but the manufacturing precision and process control difficulty increase
Solution Approach 1:
The single mask pattern is segmented into multiple functional regions, each corresponding to different structural elements (gate electrode regions, common electrode regions, gate insulation layer regions, active layer regions, and source/drain metal layer regions). By carefully designing the mask with distinct pattern segments for each layer, the invention achieves precise pattern definition for all elements using only one mask, thereby reducing device complexity while maintaining manufacturing precision.
Solution Approach 2:
The mask pattern is designed in advance to pre-establish all necessary patterns for the gate electrode, common electrode, gate insulation layer, active layer, and source/drain metal layer in a single operation. This preliminary design of the comprehensive mask pattern allows all subsequent deposition and etching steps to proceed with precise control based on the pre-defined single mask geometry, maintaining manufacturing precision while reducing the number of masks required.
Data Source
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AI summary
The present disclosure provides a thin film transistor array substrate, a method for manufacturing the same and a display device. The method includes: forming, on a substrate, a gate electrode, a common electrode, a gate insulation layer, an active layer and a source-drain metal layer; and forming, on the resultant substrate, a pixel electrode and a passivation layer by one patterning process.