TFT Array Substrate Fabrication via Single Mask Polishing
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Solution Overview
Problem
The fabrication of thin-film transistor (TFT) array substrates for LCD devices faces challenges in reducing Mura defects caused by capacitance differences between signal lines and pixel electrodes, and in preventing off-currents, which are typically associated with high fabrication costs due to the use of multiple masks.
Innovation Solution
A method is developed to fabricate TFT array substrates by forming a gate electrode, gate insulating layer, semiconductor layer, ohmic contact layer, source electrode, and drain electrode using a single mask process, with specific etching and polishing techniques to minimize capacitance variations and off-currents, including the use of a polishing slurry with controlled pH and zeta potential to optimize electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple masks are used in the fabrication process, then the characteristics of thin-film transistors can be maintained, but the fabrication cost increases
Solution Approach 1:
The patent combines multiple mask processes into a single mask process by forming the semiconductor layer, ohmic contact layer, source electrode, and drain electrode simultaneously using one mask. This merging approach reduces fabrication cost while maintaining TFT characteristics through integrated pattern formation.
Solution Approach 2:
The single mask used in the invention serves multiple functions: it defines the semiconductor layer pattern, ohmic contact layer pattern, source electrode pattern, and drain electrode pattern all at once. This multi-functional mask replaces what would traditionally require multiple separate masks, reducing overall process complexity and cost.
2Ease of manufacture
If the number of masks is reduced, then fabrication cost decreases, but the characteristics of thin-film transistors change
Solution Approach 1:
By merging the formation of semiconductor layer, ohmic contact layer, source electrode, and drain electrode into a single mask process, the patent achieves cost reduction without compromising TFT characteristics. The simultaneous patterning ensures proper alignment and electrical properties are maintained.
Solution Approach 2:
The patent employs specific etching parameters and polishing conditions to maintain TFT characteristics during the single mask process. By controlling etching depth, polishing pressure, and slurry composition, the electrical reliability of TFTs is preserved despite the simplified fabrication approach.
3Ease of manufacture
If conventional etching processes are used, then manufacturing is simpler, but Mura defects increase due to capacitance differences
Solution Approach 1:
The patent modifies etching parameters including using buffered HF solution with controlled concentration, temperature, and exposure time. These parameter changes enable precise control of etching depth to form recesses that equalize capacitance, reducing Mura defects while maintaining manufacturing feasibility.
Solution Approach 2:
The invention applies localized etching to specific regions where capacitance imbalance occurs. By forming recesses only in necessary areas beneath signal lines or pixel electrodes, the patent addresses capacitance differences locally without requiring complete process redesign, thus maintaining simplicity while reducing defects.
4Ease of manufacture
If standard polishing processes are used, then fabrication is easier, but off-current of thin-film transistors increases
Solution Approach 1:
The patent employs controlled polishing parameters including slurry pH (3-11), zeta potential (-20 to -80 mV), polishing pressure (0.1-10 kgf/cm²), and polishing speed (10-100 m/min). These parameter optimizations ensure precise removal of excess material while preserving the electrical properties of TFTs, preventing off-current increase.
Solution Approach 2:
The invention replaces aggressive mechanical etching with a controlled chemical-mechanical polishing process. This substitution allows for more precise material removal with better control over electrical properties, reducing off-current while maintaining fabrication ease through a single integrated process step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces Mura defects and prevents off-currents, thereby enhancing the electrical reliability and durability of TFTs while reducing fabrication costs by minimizing the number of masks required.
Implementation Method 1
one of the plurality of metal layer patterns is etched through a polishing process
Implementation Method 2
forming a photoresist pattern on the third metal layer using a second mask
Data Source
AI summary
A method of fabricating a thin-film transistor (TFT) array substrate including forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and forming a source electrode and a drain electrode comprising a plurality of metal layer patterns on the ohmic contact layer, in which the semiconductor layer, the ohmic contact layer, the source electrode and the drain electrode are formed through a single mask process, and one of the plurality of metal layer patterns is etched through a polishing process to form the source electrode and the drain electrode.