TFT Array Substrate with Segmented Common Electrodes

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Solution Overview

Problem

In liquid crystal displays (LCDs), forming two electric field generating electrodes on a single thin-film transistor (TFT) array substrate can lead to delayed signal transmission due to the common electrode being integrally formed as a single unit, and the passivation layer is prone to over-etching, causing electrode protrusion issues.

Innovation Solution

A method involving the formation of gate lines and data lines on a substrate, followed by the deposition of organic layers, electrodes, and passivation layers, with the use of photosensitive layer patterns and cover layers to create cutout patterns in the electrodes and passivation layers, ensuring precise etching and preventing over-etching of the passivation layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the common electrode is integrally formed as a single unit, then the manufacturing process is simplified, but signal transmission is delayed

Engineering Contradiction:

Improveease of forming common electrodeVSAvoidsignal transmission delay

Core Design Contradiction:

Ease of manufactureVSLoss of time

Solution Approach 1:

The common electrode is divided into multiple separate common electrode patterns rather than being formed as a single integral unit. This segmentation allows signals to reach different regions simultaneously through multiple parallel paths, reducing signal transmission delay while maintaining manufacturing simplicity through patterned deposition processes

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If etching is performed to create cutout patterns in electrodes, then electrode functionality is improved, but passivation layer over-etching occurs causing electrode protrusion

Engineering Contradiction:

Improveelectrode pattern functionalityVSAvoidpassivation layer etching control

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

A cover layer is formed over the passivation layer before etching the electrode patterns. This preliminary protective action prevents the etchant from reaching and over-etching the passivation layer, allowing precise cutout patterns to be created in the electrodes without compromising the underlying passivation structure

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The cover layer serves as an intermediary protective barrier between the etching process and the passivation layer. It allows the etching to proceed cleanly to create electrode cutouts while preventing the etchant from attacking the passivation layer, thus maintaining manufacturing precision

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the effective manufacturing of TFT array substrates with two electric field generating electrodes without increasing costs and prevents passivation layer over-etching, maintaining electrode coverage and improving signal transmission efficiency.

Implementation Method 1

providing photosensitive layer patterns on the cover layer, providing first cutout patterns in the cover layer and second cutout patterns in the second electrode by etching the cover layer and the second electrode using the photosensitive layer patterns as an etch mask

Methodology Applied

Scientific EffectPhotochemical etching: Photopolymerisation

Implementation Method 2

providing a plurality of third cutout patterns in the passivation layer using the first cover layer as an etch mask

Methodology Applied

Scientific EffectPhysical etching: Ablation

Data Source

PatentUS20150044797A1Methods of manufacturing thin-film transistor array substrate and liquid crystal display

Publication Date: 2015.02.12 LONESTAR CRYSTAL DISPLAY LLC

AI summary

A method of manufacturing a thin film transistor array substrate includes providing a plurality of gate lines and a plurality of data lines on a first substrate, providing an organic layer on the gate lines and the data lines, providing a first electrode on the organic layer, providing a passivation layer on the first electrode, providing a second electrode on the passivation layer, providing a first cover layer on the second electrode to cover the second electrode, providing a plurality of photosensitive layer patterns on the first cover layer, providing a plurality of first cutout patterns in the first cover layer and a plurality of second cutout patterns in the second electrode using the photosensitive layer patterns as an etch mask, and providing a plurality of third cutout patterns in the passivation layer using the first cover layer as an etch mask.