Bottom-Gate TFT Channel Gate Contact for OLED Substrate Bias
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Solution Overview
Problem
In OLED display devices, bottom-gate thin film transistors (TFTs) experience increased threshold voltage and deteriorated subthreshold slope due to substrate bias, which affects the performance and efficiency of the devices.
Innovation Solution
The solution involves electrically connecting the channel region and gate electrode through an interconnection portion and a gate-body contact portion, reducing the influence of substrate bias and improving the subthreshold slope, thereby allowing a large drain current to be obtained at a low gate voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a bottom-gate TFT structure is used in OLED display devices, then the device can be fabricated with simple processes and solid materials, but the substrate bias causes increased threshold voltage and deteriorated subthreshold slope
Solution Approach 1:
The semiconductor layer is segmented into distinct channel region, source region, and drain region with different doping concentrations. The channel region has lower doping concentration to reduce substrate bias influence, while source and drain regions have higher doping concentrations for efficient carrier injection and extraction, resolving the threshold voltage control issue while maintaining fabrication simplicity
Solution Approach 2:
Different regions of the semiconductor layer are assigned different local properties: the channel region has low doping concentration (1×10^16 to 1×10^18 atoms/cm³) to minimize substrate bias effects and maintain low threshold voltage, while source and drain regions have high doping concentration (1×10^19 to 1×10^21 atoms/cm³) for effective carrier transport, achieving both easy manufacture and reliable voltage control
2Device complexity
If a bottom-gate TFT structure is used, then the device structure is simple, but the subthreshold slope deteriorates due to substrate bias
Solution Approach 1:
The semiconductor layer is divided into channel region, source region, and drain region with optimized doping profiles. The channel region's low doping concentration reduces the impact of substrate bias on the electric field distribution, improving the subthreshold slope while keeping the overall bottom-gate structure simple
Solution Approach 2:
The doping concentration parameter is optimized differently for each region: the channel region uses low doping (1×10^16 to 1×10^18 atoms/cm³) to reduce substrate bias influence and improve subthreshold slope, while source and drain regions use high doping (1×10^19 to 1×10^21 atoms/cm³) for efficient carrier injection, achieving improved reliability without increasing structural complexity
3Power
If the channel region is connected to the gate electrode, then a large drain current can be obtained at low gate voltage, but additional interconnection portions and contact portions are required
Solution Approach 1:
The gate-body contact portion is merged with the existing gate electrode structure, and the interconnection portion is integrated into the source and drain electrode formation process. This combining approach enables direct connection between the channel region and gate electrode for high drain current operation while minimizing additional structural complexity
Solution Approach 2:
The gate electrode structure serves multiple functions: it provides the gate control function, acts as part of the interconnection structure for the channel region, and forms the gate-body contact portion. This multi-functionality enables high power efficiency through direct channel-gate connection while avoiding significant increases in device complexity
Data Source
AI summary
A thin film transistor (TFT), a method of fabricating the same, and a display device including the TFT, are provided. In the TFT, a channel region is connected to a gate electrode so that the influence of a substrate bias is reduced or eliminated. Thus, the threshold voltage of the TFT is reduced, a subthreshold slope can be improved, and a large drain current can be obtained at a low gate voltage.