Thin Film Transistor Data Line Etching via Halftone Mask
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Solution Overview
Problem
The 4-mask process in LCD panel manufacturing results in exposed copper surfaces reacting with dry etching gases, forming copper compounds that affect subsequent etching steps, leading to abnormal taper angles and serrated data lines, which impair step coverage and yield.
Innovation Solution
A manufacturing method for thin film transistors using a halftone mask method to form a photoresist layer with specific thickness and width profiles, allowing for a 4-mask process that avoids jagged edges by controlling the etching of data lines and source/drain layers, ensuring normal taper angles and improved step coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a 4-mask process is used to reduce manufacturing cost, then the cost of the array process is reduced, but the copper compounds are formed during dry etching which affect subsequent etching processes and create abnormal taper angles and serrated data lines
Solution Approach 1:
The patent applies preliminary action by forming a protective layer on the copper surface before the dry etching process. This protective layer prevents copper oxidation during the etching steps, thereby avoiding the formation of copper compounds that would otherwise create jagged edges and abnormal taper angles. The protective layer is formed in advance to prevent the harmful effect rather than correcting it afterward.
Solution Approach 2:
The patent introduces an intermediary substance (protective layer) between the copper surface and the dry etching environment. This intermediary layer acts as a barrier that prevents direct interaction between the copper and etching gases, thereby preventing copper compound formation while allowing the etching process to proceed. This resolves the contradiction by mediating the harmful interaction.
2Productivity
If dry etching is performed on copper surfaces, then the data line and source/drain structures are formed, but copper compounds are formed on the exposed copper surfaces which affect the next etching process
Solution Approach 1:
The protective layer is formed preliminarily before the dry etching process to prevent copper oxidation. This preliminary protection ensures that the copper surface remains clean and reactive for subsequent wet etching steps, maintaining etching process stability and reliability throughout the manufacturing sequence.
Solution Approach 2:
The protective layer serves as an intermediary that allows the dry etching process to proceed efficiently on the overlying layers while protecting the copper surface underneath. This intermediary layer enables high productivity in the dry etching steps while simultaneously ensuring reliability by preventing copper compound formation that would disrupt subsequent processes.
3Ease of manufacture
If the copper surface is exposed during the 4-mask process, then the manufacturing process can be completed, but the step coverage is affected due to abnormal taper angles and serrated data lines
Solution Approach 1:
The protective layer is applied preliminarily to prevent copper oxidation during the 4-mask process. By preventing the formation of copper compounds from the outset, the subsequent wet etching steps can proceed uniformly, producing smooth data line edges and normal taper angles, thereby ensuring good step coverage while completing the manufacturing process.
Solution Approach 2:
The protective layer acts as an intermediary that enables the 4-mask process to be completed while maintaining manufacturing precision. It mediates between the need to expose copper surfaces for patterning and the need to prevent oxidation, allowing both process completion and good step coverage to be achieved simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method prevents the formation of jagged edges on copper data lines and source/drain layers, enhancing the step coverage and yield by maintaining the intended shape and structure during the etching process.
Implementation Method 1
performing a half-tone mask method to etch the photoresist material film layer, forming a photoresist layer
Implementation Method 2
performing a 4-mask process to etch the first substrate, forming the data line on the gate insulating layer, forming the source and the drain on the active layer
Data Source
AI summary
The disclosure provides a manufacturing method for a thin film transistor, wherein a manufacturing method for a data line and a source/drain specifically includes: S21: respectively manufacturing a data line material film layer and a source/drain material film layer; S22: manufacturing a photoresist material film layer; S23: performing a half-tone method to etch the photoresist material film layer, forming a photoresist layer, and obtaining a first etching substrate; S24: performing a 4-mask process to etch the first substrate, forming the data line on a gate insulating layer, forming the source and the drain on an active layer, and forming a the back channel between the source and the drain to obtain the thin film transistor. The disclosure further provides a manufacturing method for an array substrate, wherein the manufacturing method for an array substrate includes the above-mentioned manufacturing method for a thin film transistor.