Thin-Film Transistor Gate Alignment for Higher Turn-On Current
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Solution Overview
Problem
The existing methods for fabricating top-gate thin film transistors result in insufficient turn-on current due to the lack of a gate on the edge of the gate insulating layer pattern, affecting the electrical characteristics and display effect of display devices.
Innovation Solution
A method involving the sequential deposition of a light shielding layer, active layer, gate insulating layer, and gate layer, followed by wet etching and dry etching processes to form precise patterns, ensuring the entire active layer is under the gate insulating layer, with the gate layer pattern acting as a mask for dry etching and metalization of the non-channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wet etching is used to fabricate the gate pattern, then the etching process is simple and cost-effective, but the gate pattern becomes smaller than the gate insulating pattern resulting in misalignment
Solution Approach 1:
The patent segments the gate pattern fabrication into two distinct steps: first forming the gate insulating layer pattern with precise dimensions, then forming the gate layer pattern separately. This segmentation allows each layer to be optimized independently - the gate insulating layer provides the precise boundary definition while the gate layer is formed to match it, eliminating the under-etching problem of conventional wet etching.
Solution Approach 2:
The gate insulating layer pattern is formed in advance before the gate layer pattern. This preliminary action establishes the precise boundary definition that the gate layer must follow, ensuring that the gate layer is formed with exact alignment to the gate insulating layer edges, thereby preventing misalignment issues.
2Ease of manufacture
If the gate pattern is smaller than the gate insulating pattern, then the wet etching process is effective, but the edge regions of the active layer are not regulated by the gate resulting in insufficient turn-on current
Solution Approach 1:
The patent employs dry etching processes (plasma etching) to fabricate both the gate insulating layer pattern and the gate layer pattern. This hydraulic/gas-phase approach allows for precise pattern transfer with vertical sidewalls and excellent dimensional control, ensuring the gate layer pattern completely coincides with the gate insulating layer pattern, thereby providing gate regulation over the entire active layer including edge regions.
3Manufacturing precision
If dry etching is used to form the gate insulating layer pattern, then the pattern precision is improved, but the process complexity increases
Solution Approach 1:
The patent merges the advantages of different etching approaches by using dry etching specifically for the gate insulating layer pattern formation where precision is critical, while using wet etching for the gate layer pattern formation where simplicity is advantageous. This selective combination optimizes both precision and process simplicity by applying each etching method to the step where it provides the greatest benefit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures complete alignment of the gate and insulating layer patterns, enhancing the turn-on current and electrical characteristics of the thin film transistor, thereby improving the display effect of the device.
Implementation Method 1
wet etching the gate layer to form a gate layer pattern
Implementation Method 2
dry etching the gate insulating layer to form a gate insulating layer pattern
Implementation Method 3
depositing a light shielding layer on the substrate
Data Source
AI summary
The present disclosure provides a method for fabricating a thin film transistor substrate, which includes: sequentially depositing a light shielding layer pattern, a buffer layer, an active layer pattern, a gate insulating layer, and a gate layer; wet etching the gate layer to form a gate layer pattern with a photoresist; stripping off the photoresist; forming a protective layer covering the gate layer pattern; etching the gate insulating layer to form a gate insulating layer pattern; and metalizing a non-channel region of the active layer pattern. This method can ensure that an orthographic projection of the gate layer pattern on the substrate completely coincides with that of the gate insulating pattern. Therefore, the entire active layer pattern is regulated by the gate layer pattern, thereby improving a turn-on current of a thin film transistor.