TFT Substrate Gate-Scan Layout for Large LCD Pixel Charging
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Solution Overview
Problem
Large-size LCDs face insufficient pixel charging due to excessive scan line loading, which affects their performance.
Innovation Solution
A thin film transistor substrate is designed with a specific structure, including a substrate, metal layers, a semiconductor with an active region, and insulating layers. The gate pattern overlaps the active region, and the scan line pattern of the second metal layer is electrically connected to the gate pattern through an opening in the insulating layer, reducing scan line load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional LCD structure is used for large-size panels, then the display area is increased, but the pixel charging becomes insufficient due to excessive scan line loading
Solution Approach 1:
The gate electrode is divided into two separate metal layers (first metal layer and second metal layer), with the gate pattern in the first layer and scan line pattern in the second layer. This segmentation allows independent optimization of gate control and scan line routing, reducing scan line loading and improving pixel charging efficiency in large-size panels
Solution Approach 2:
The gate electrode is extended into a third dimension by creating a stacked structure where the first metal layer with gate pattern is positioned at a different vertical level than the second metal layer with scan line pattern. The insulating layer with opening provides vertical electrical connection, enabling the gate to exert control influence in the vertical dimension while reducing horizontal scan line load
Data Source
AI summary
A thin film transistor substrate includes a substrate, a first metal layer disposed on the substrate, a second metal layer disposed on the first metal layer, a semiconductor disposed between the substrate and the first metal layer, and a first insulating layer disposed between the first metal layer and the second metal layer. The first metal layer includes a gate pattern, the second metal layer includes a scan line pattern, the semiconductor includes an active region, and the first insulating layer includes a first opening. The gate pattern overlaps the active region, and the scan line pattern of the second metal layer is electrically connected to the gate pattern of the first metal layer through the first opening in the first insulating layer.