Thin Film Transistor Substrate via Halftone Mask
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Solution Overview
Problem
The existing methods for manufacturing thin film transistor matrix substrates require a high number of photo masks, leading to increased production costs and complexity in controlling the thickness and taper angle of the photo resist layer, which affects the etching process.
Innovation Solution
A method that reduces the number of photo masks required to three by employing a halftone photo mask with gray level exposure distribution to define different thicknesses of the photo resist layer, allowing for self-alignment etching and reducing the number of etching steps, thereby simplifying the process and maintaining device properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the number of photo masks is reduced to save cost and time, then production cost and manufacturing time are reduced, but the control precision of photo resist layer thickness and taper angle deteriorates
Solution Approach 1:
The photo resist layer is segmented into multiple thickness regions using gray level exposure, where different areas receive different amounts of light exposure to create varying thickness profiles. This allows the single photo resist layer to serve multiple functional purposes that would traditionally require separate masking steps.
Solution Approach 2:
Different regions of the photo resist layer are given different local qualities (thicknesses) through gray level exposure. The channel region receives one exposure level while source/drain regions receive another, allowing each region to be optimized for its specific function without requiring separate masks.
2Object-affected harmful factors
If the photo resist layer thickness is reduced to protect the channel, then plasma damage is reduced, but the etching selectivity and control deteriorate
Solution Approach 1:
The photo resist layer is designed with different local thicknesses: thinner over the channel region to minimize plasma damage and protect the semiconductor, and thicker over the source/drain regions to maintain adequate etching protection and selectivity. This spatial variation in thickness allows simultaneous optimization for both protection and control.
Solution Approach 2:
The gray level exposure technique converts what would normally be a control difficulty (varying thickness) into a beneficial feature, where the thinner photo resist over the channel becomes a protective measure against plasma damage, while the thicker regions elsewhere provide the necessary etching protection.
3Manufacturing precision
If the taper angle of the photo resist layer is controlled to improve etching results, then etching precision is improved, but the process complexity increases
Solution Approach 1:
The taper angle control is segmented by region through gray level exposure, where the photo resist is formed with different angles in different areas. This allows optimized taper angles for specific regions without requiring additional processing steps or masks.
Solution Approach 2:
The mechanical or chemical modification approaches for controlling taper angle are replaced by an optical approach (gray level exposure). By varying the light intensity during exposure, the desired taper angles are achieved directly during the photo resist formation step, eliminating the need for subsequent mechanical or chemical adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the production cost, minimizes damage to transistor channels during etching, and enhances the optical current generation while reducing plasma damage, resulting in more competitive and efficient manufacturing of inverted staggered back-channel-protected thin film transistor matrix substrates.
Implementation Method 1
A halftone photo mask is used in the second photo mask process. A halftone gray level exposure distribution is employed to expose and develop a PR layer, thereby defining a channel, gate electrode through holes, signal electrode through holes, and conductive pads with different thickness of the PR layer.
Data Source
AI summary
A method of manufacturing a thin film transistor matrix substrate is provided. The first photo-mask process is used to define a gate electrode and a signal electrode. The second photo-mask process is used to obtain different thickness of a PR layer in different regions for forming a channel, gate electrode through holes, signal electrode through holes and conductive pads. The third photo-mask process is used to define a source, a drain, an upper signal electrode, a pixel electrode, gate electrode pads and signal electrode pads.