TFT-LCD Panel Electrode Layout for Parasitic Capacitance Compensation
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Solution Overview
Problem
Parasitic capacitance in TFT-LCDs affects display quality due to disorderly deflection of liquid crystal molecules, which existing technologies have not adequately addressed.
Innovation Solution
Incorporating additional electrodes on the opposite substrate that generate parasitic capacitance in series with the original parasitic capacitance on the array substrate, effectively neutralizing the original parasitic capacitance by connecting them in series, thereby reducing the overall parasitic effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional electrodes are added to the opposite substrate to generate compensating parasitic capacitance, then the display quality is improved by offsetting parasitic effects, but the device complexity increases due to additional electrode structures and wiring
Solution Approach 1:
The patent converts the harmful parasitic capacitance generated by signal lines into a beneficial effect by introducing additional electrodes that generate compensating parasitic capacitance. These additional parasitic capacitances are connected in series with the original parasitic capacitance, creating an offsetting effect that reduces the net parasitic impact on liquid crystal molecule deflection and improves display quality.
Solution Approach 2:
The additional electrodes act as intermediary elements between the signal lines and the liquid crystal layer. By positioning these electrodes on the opposite substrate and connecting them through constant voltage signal lines, the patent creates intermediate parasitic capacitance structures that mediate and offset the harmful effects of the original parasitic capacitance from the data and gate lines.
2Reliability
If the orthographic projection of additional electrodes overlaps with overlap regions of signal lines, then the parasitic capacitance offsetting effect is maximized, but the manufacturing precision requirements increase due to alignment constraints
Solution Approach 1:
The patent applies local quality by positioning additional electrodes with specific orthographic projections that overlap with specific overlap regions of signal lines. Each additional electrode is strategically located to compensate for parasitic capacitance in its corresponding region, creating localized compensation zones that collectively improve overall display quality while maintaining manageable alignment requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The additional parasitic capacitance offsets the original parasitic capacitance, leading to improved display quality by minimizing parasitic effects and enhancing the display performance.
Implementation Method 1
the coupling of TFT, gate lines, data lines and so on normally generate parasitic capacitance, which affects the liquid crystal capacitance
Data Source
Figure 1
Figure 2~4A
Figure 4B~4C
AI summary
A display panel comprises an array substrate (10) comprising a first substrate (11), a gate line (12), a data line (13), and a thin film transistor (14) with a gate electrode (141), a source electrode (142) and a drain electrode (143) on a surface of the first substrate (11); and a plurality of sub-pixel regions (16) on the array substrate (10) defined by the gate line (12) and the data line (13); and an opposite substrate (20) comprising a second substrate (21), a plurality of additional electrodes (22) arranged on a side of the second substrate (21) facing the array substrate (10); at least on sub-pixel region (16) comprises at least one of: a first overlap region (31) at an intersection region by the gate line (12) and the data line (13), a second overlap region (32) defined by an overlapping region between the gate electrode (141) and the source electrode (142), or a third overlap region (33) defined by an overlapping region between the gate electrode (141) and the drain electrode (143); and an orthographic projection of the additional electrodes (22) on the first substrate (11) substantially overlaps with orthographic projections of at least one of the first overlap region (31), the second overlap region (32), or the third overlap region (33) on the first substrate (11).