TFT-LCD MOS Transistor Mask Reduction via Dual-Island Ion Implantation
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Solution Overview
Problem
The conventional TFT-LCD fabrication process requires multiple photomasks, increasing process time and cost without significantly affecting yield.
Innovation Solution
A method is introduced that reduces the number of photomasks needed by performing simultaneous ion implantation for both NMOS and PMOS devices, using a single patterned mask to form source/drain regions and gates, thereby eliminating the need for additional photolithography steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a patterned mask is formed to cover the PMOS device before performing NMOS channel-doping, then the NMOS device can be doped with ions, but the process time and cost are increased due to requiring additional photomasks
Solution Approach 1:
The patent combines the formation of source/drain regions and channel doping into a single ion implantation step. By using a dual-layer mask structure where the first mask defines source/drain regions and the second mask defines channel regions, both doping operations are performed simultaneously in one process step, eliminating the need for separate masking and doping steps for channel doping.
Solution Approach 2:
The patent forms the channel doping regions during the source/drain region formation step itself. The second mask layer is formed preliminarily to define channel regions before the ion implantation that creates source/drain regions, ensuring that channel doping is already in place before transistor operation, thus eliminating subsequent channel doping steps.
2Reliability
If a patterned mask is formed to cover the PMOS device before performing NMOS channel-doping, then the NMOS device can be doped with ions, but the manufacturing cost is increased due to requiring additional photomasks
Solution Approach 1:
The patent merges the source/drain region formation and channel doping operations into a single ion implantation process. The dual-mask structure allows both source/drain and channel regions to be defined and doped in one step, reducing the total number of photomasks and process steps required, thereby lowering manufacturing costs.
Solution Approach 2:
The first mask layer serves multiple functions: it defines the source/drain regions for both NMOS and PMOS devices and simultaneously serves as a mask for channel doping. This multi-functional mask reduces the total number of masks required compared to conventional separate masking approaches.
3Manufacturing precision
If separate masks are used for forming source/drain regions and channel doping, then doping precision can be maintained, but the device complexity increases
Solution Approach 1:
The patent segments the mask structure into two functional layers: a first mask layer for defining source/drain regions and a second mask layer for defining channel regions. This segmentation allows each mask to be optimized for its specific function while maintaining overall process simplicity through simultaneous ion implantation.
Solution Approach 2:
The patent combines multiple doping operations (source/drain doping and channel doping) into a single ion implantation step. Although the mask structure is segmented into two layers, the actual doping process is merged into one step, reducing process complexity compared to sequential separate doping operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases the fabrication time and cost while maintaining yield, improving competitiveness and productivity by reducing the number of photomasks required in the TFT-LCD process.
Implementation Method 1
performing a first ion implantation process to dope ions into both of the first island and the second island
Implementation Method 2
performing an excimer laser annealing process to enable amorphous silicon layer to be transformed into a polysilicon layer
Data Source
AI summary
A method of forming a display device is provided. The method includes the following steps: providing a substrate which includes a driving circuit region and a pixel region; forming a first island and a second island in the driving circuit region on the substrate with a semiconductor material; performing a first ion implantation process to dope ions into both of the first island and the second island; forming a first patterned mask on the substrate to cover the second island and expose a part of the first island; performing a second ion implantation process by using the first patterned mask as a mask to form a first source/drain region in the first island; removing the first patterned mask; forming a first gate and a second gate on the first island and the second island respectively; forming a second patterned mask on the substrate to cover the first island and expose a part of the second island; and performing a third ion implantation process by using both of the second patterned mask and the second gate as a mask to form a second source/drain region in the second island. The first island, the first source/drain region, and the first gate form a NMOS device, and the second island, the second source/drain region, and the second gate form a PMOS device.


