Thin Film Transistor Metal Catalyst Crystallization
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Solution Overview
Problem
Existing methods for crystallizing amorphous silicon into polycrystalline silicon for thin film transistors (TFTs) face challenges such as high temperature annealing damaging substrates, expensive laser equipment requirements, and increased leakage current due to uncontrolled metal catalyst concentration in the channel region, degrading electrical properties.
Innovation Solution
A method involving a semiconductor layer with distinct first and second metal catalyst crystallization regions, where the second region has larger crystal grains and a smaller remaining metal catalyst concentration, achieved by controlled diffusion of metal catalysts using a capping layer and subsequent annealing, minimizing metal catalyst presence in the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solid phase crystallization (SPC) method is used to crystallize amorphous silicon layer, then the substrate can be annealed at high temperature for complete crystallization, but the substrate suffers great damage due to high temperature annealing for long period
Solution Approach 1:
A metal catalyst layer is deposited on the amorphous silicon layer before crystallization. This preliminary action enables the silicon to crystallize at lower temperatures through metal-induced crystallization, avoiding the need for high-temperature annealing that damages the substrate.
Solution Approach 2:
A capping layer is introduced as an intermediary between the metal catalyst and the amorphous silicon layer. This capping layer controls the diffusion of metal catalyst into the silicon, enabling crystallization while preventing excessive metal contamination that would increase leakage current.
2Loss of time
If excimer laser annealing (ELA) method is used to crystallize amorphous silicon layer, then crystallization can be achieved at high temperature in short time, but expensive laser apparatuses are required and protrusions are formed in the surface
Solution Approach 1:
The patent replaces the complex laser apparatus with a simpler thermal annealing process. By using metal-induced crystallization with controlled thermal annealing, the expensive laser equipment is substituted while achieving comparable or better crystallization results without surface protrusions.
3Temperature
If metal catalyst is used to crystallize amorphous silicon layer, then crystallization temperature and time are reduced, but metal catalyst remains in channel region increasing leakage current
Solution Approach 1:
The capping layer serves as an intermediary that controls metal catalyst diffusion. It allows sufficient metal catalyst to reach the amorphous silicon layer for crystallization, while preventing excessive metal catalyst from remaining in the channel region, thus reducing leakage current.
Solution Approach 2:
The patent creates different metal catalyst concentrations in different regions. The capping layer thickness is controlled to allow metal diffusion to the silicon layer for crystallization, while the channel region maintains lower metal concentration to minimize leakage current.
4Reliability
If metal catalyst concentration in channel region is increased to ensure complete crystallization, then crystallization is more effective, but leakage current increases degrading electrical properties
Solution Approach 1:
The capping layer acts as a diffusion barrier that precisely controls metal catalyst concentration. It ensures enough metal reaches the silicon for complete crystallization while limiting excess metal from entering the channel region, thereby maintaining good electrical properties.
Solution Approach 2:
The patent optimizes the capping layer thickness parameter to control metal catalyst diffusion. By adjusting this parameter, the metal concentration in the channel region is controlled to balance crystallization effectiveness with acceptable leakage current levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage current and improves electrical properties of TFTs, resulting in better performance and suitability for organic light emitting diode (OLED) display devices by minimizing metal catalyst presence and enhancing crystal grain size.
Implementation Method 1
The MIC method includes bringing a metal, such as nickel (Ni), palladium (Pd), gold (Au), or aluminum (Al), into contact with an a-Si layer or injecting the metal into the a-Si layer to induce a phase transition from the a-Si layer to a poly-Si layer
Implementation Method 2
A method involving a semiconductor layer with distinct first and second metal catalyst crystallization regions, where the second region has larger crystal grains and a smaller remaining metal catalyst concentration, achieved by controlled diffusion of metal catalysts using a capping layer and subsequent annealing
Implementation Method 3
The SPC method includes annealing an a-Si layer for several hours to several tens of hours at temperatures below 700° C.
Data Source
AI summary
A thin film transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate and including source and drain regions, each having a first metal catalyst crystallization region and a second metal catalyst crystallization region, and a channel region having the second metal catalyst crystallization region, a gate electrode disposed in a position corresponding to the channel region of the semiconductor layer, a gate insulating layer interposed between the semiconductor layer and the gate electrode to electrically insulate the semiconductor layer from the gate electrode, and source and drain electrodes electrically insulated from the gate electrode and electrically connected to the source and drain regions, respectively. An OLED display device includes the thin film transistor and a first electrode, an organic layer, and a second electrode electrically connected to the source and drain electrodes.