Thin Film Transistor Multi-Layer Source Drain Structure
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Solution Overview
Problem
Conventional thin film transistor manufacturing processes often result in incomplete etching of the channel, leading to bridge connections between the source and drain, which causes defectiveness in display devices, such as bright spots and lowers product quality.
Innovation Solution
The source and drain layers are formed in different layers, with the drain and gate layers in the same layer, and a composite layer extending over the gate insulating layer and part of the drain layer to prevent bridge connections, using materials like molybdenum, aluminum, and indium gallium zinc oxide, and employing specific patterning processes to ensure complete disconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source and drain are formed in the same layer with a gap or trench therebetween, then the manufacturing process is simpler, but the source and drain may be bridge connected due to incomplete etching
Solution Approach 1:
The patent transitions from a planar same-layer structure to a multi-layer vertical structure. The source layer and drain layer are positioned in different layers, with the drain layer and gate layer in the same layer. This dimensional change eliminates the need for complete etching through the channel, as the source and drain are naturally separated by the gate structure in the same layer, preventing bridge connections while simplifying the manufacturing process.
Solution Approach 2:
The patent segments the source and drain into different layers rather than keeping them in the same layer. The drain layer is positioned in the same layer as the gate layer, while the source layer is in a different layer above or below it. This segmentation allows the gate to act as a physical barrier preventing bridge connections between source and drain, eliminating the need for complete channel etching.
2Ease of manufacture
If conventional etching processes are used to form source and drain with a gap, then the process is straightforward, but the channel is not completely etched leading to bridge connections
Solution Approach 1:
The patent uses a multi-layer configuration where the drain layer and gate layer are in the same layer, while the source layer is in a different layer. This vertical separation in another dimension eliminates the requirement for complete horizontal etching through the channel, as the gate structure physically prevents bridge connections between source and drain.
Solution Approach 2:
The gate layer acts as an intermediary structure that physically separates and prevents bridge connections between the source and drain layers. By positioning the drain layer in the same layer as the gate layer, the gate serves as a mediator that ensures complete disconnection without requiring aggressive etching processes.
3Device complexity
If source and drain are in the same layer, then the structure is simpler, but product quality grade is lowered due to bright spot defects
Solution Approach 1:
The patent resolves the contradiction by moving the source and drain to different layers vertically, while keeping the drain layer in the same layer as the gate layer. This multi-layer configuration prevents bridge connections and eliminates bright spot defects, improving product quality without significantly increasing device complexity, as it utilizes the vertical dimension already present in TFT structures.
Solution Approach 2:
The patent segments the source and drain into different layers to prevent bridge connections. The drain layer is positioned with the gate layer in the same layer, while the source layer is in a different layer. This segmentation physically prevents the formation of bridge connections, eliminating bright spot defects and maintaining high product quality grades.
Data Source
AI summary
A thin film transistor, an array substrate, a manufacturing method and a display device are provided. The thin film transistor includes a substrate and a gate layer, a source layer and a drain layer disposed on the substrate. The source layer and the drain layer are disposed in different layers and the drain layer and the gate layer are disposed in same and one layer.