TFT Passivation Layer Etching Profile Control
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Solution Overview
Problem
In the fabrication of Thin-Film Transistor (TFT) array substrates for Liquid-Crystal Display (LCD) devices, the etching profile of the passivation layer and gate insulating layer is often square or inverted tapered when using high-speed dry etching, leading to point defects due to the conductive layer being divided or cut, which is not effectively controlled by existing methods.
Innovation Solution
A TFT with a passivation layer having a multiple-layer structure comprising a first sublayer with a lower etch rate and a second sublayer with a higher etch rate, where the second sublayer is side-etched to maintain a tapered etching profile, preventing the conductive layer from being divided or cut, and the thickness of the second sublayer is equal to or less than the conductive layer, ensuring controlled etching profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the etch rate is raised by changing the etching condition in a dry etching process, then the production capacity of the etching apparatus is improved, but the etching profile of the contact holes becomes square or inverted tapered, causing the conductive layer to be divided or cut
Solution Approach 1:
The passivation layer is divided into multiple sublayers (first sublayer and second sublayer) with different etch rates. This segmentation allows each sublayer to be etched at different rates, enabling the formation of a tapered profile even when the overall etch rate is high, thus preventing conductive layer division while maintaining high productivity
Solution Approach 2:
Different sublayers of the passivation layer are assigned different etch rate characteristics. The first sublayer has a lower etch rate while the second sublayer has a higher etch rate, creating local quality differences that enable precise control of the etching profile shape independent of the overall etch rate
2Manufacturing precision
If the etch rate of the passivation layer and gate insulating layer is set to be approximately equal to or less than the etch rate of the photoresist film, then the etching profile is tapered, but the production capacity of the etching apparatus is reduced
Solution Approach 1:
The passivation layer is segmented into sublayers with different etch rates, allowing the overall etch rate to be increased for higher productivity while the specific sublayer etch rates are controlled to maintain tapered profiles
Solution Approach 2:
The etch rate parameters of different passivation layer sublayers are independently controlled and optimized. By adjusting the etch rate of each sublayer separately, the system achieves both high overall productivity and precise tapered profile control
Data Source
AI summary
A thin-film transistor includes a gate layer, a gate insulting layer, a semiconductor layer, a drain layer, a passivation layer (each of which being formed on or over an insulating substrate), and a conductive layer formed on the passivation layer. The conductive layer is connected to the gate layer or the drain layer by way of a contact hole penetrating at least the passivation layer. The passivation layer has a multiple-layer structure comprising at least a first sublayer and a second sublayer stacked, the first sublayer having a lower etch rate than that of the second sublayer. The first sublayer is disposed closer to the substrate than the second sublayer. The second sublayer has a thickness equal to or less than that of the conductive layer. The shape or configuration of the passivation layer and the underlying gate insulating layer can be well controlled in the etching process, and the conductive layer formed on the passivation layer is prevented from being divided.