TFT Conductive Pattern Layout for LCD Feed-Through Reduction
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Solution Overview
Problem
Traditional LCD devices suffer from parasitic capacitance between the gate and drain electrodes, leading to a feed-through effect that causes image flicker, reducing display quality.
Innovation Solution
The design includes a specific shape and arrangement of conductive patterns and electrode layers on the substrates, with a conductive pattern having distinct widths and positions relative to the gate electrode line, reducing parasitic capacitance and minimizing the feed-through effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional thin film transistor structure is used with gate electrode and drain electrode, then the device can be manufactured with standard processes, but parasitic capacitance occurs between gate and drain electrodes causing feed-through effect and image flicker
Solution Approach 1:
The patent extracts and removes the problematic parasitic capacitance effect by reconfiguring the electrode arrangement. Specifically, the gate electrode is extended to overlap with the active layer region, and the drain electrode is positioned to minimize overlap with the gate electrode, thereby extracting the harmful parasitic capacitance from the traditional transistor structure while maintaining manufacturability.
Solution Approach 2:
The patent applies dimensional changes by extending the gate electrode in the first direction to overlap with the active layer, and positioning the drain electrode in a configuration that minimizes parasitic capacitance. This spatial reconfiguration in multiple dimensions allows the structure to achieve both manufacturability and reduced parasitic effects.
2Device complexity
If gate driver is fabricated directly on LCD panel using GOA technique, then device complexity is reduced, but parasitic capacitance between gate and drain electrodes still causes feed-through effect
Solution Approach 1:
The patent applies local quality by creating a specific electrode configuration in the pixel region where the gate electrode overlaps with the active layer, and the drain electrode is positioned to minimize parasitic capacitance. This localized structural optimization addresses the feed-through effect in the critical pixel area while maintaining the integrated GOA structure throughout the panel.
Solution Approach 2:
The patent introduces an intermediary insulating layer between the gate electrode and the active layer/drain electrode region. This intermediary layer acts as a mediator to reduce the parasitic capacitance coupling between the gate and drain electrodes, thereby mitigating the feed-through effect while preserving the integrated gate driver structure.
3Ease of manufacture
If conventional electrode arrangement is used to simplify manufacturing, then production is easier, but display quality deteriorates due to image flicker from parasitic capacitance
Solution Approach 1:
The patent applies asymmetry by creating an asymmetric electrode configuration where the gate electrode extends to overlap with the active layer region, while the drain electrode is positioned asymmetrically to minimize overlap with the gate electrode. This asymmetric arrangement reduces parasitic capacitance and improves display quality while remaining compatible with conventional manufacturing processes.
Data Source
AI summary
The electronic device includes a substrate; an active layer disposed above the first substrate; a first signal line disposed above the substrate; and a conductive pattern. The conductive pattern is in electrical contact with the active layer, wherein the conductive pattern includes a first side extending in a first direction, a second side extending in the first direction, and a third side connected between the first side and the second side, and wherein the third side includes a part that the part is not parallel to the first direction and not perpendicular to the first direction, and the part is located out of the first signal line.