TFT Pixel Structure Fabrication via Laser Ablation
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Solution Overview
Problem
The high cost of fabricating pixel structures in TFT LCDs due to the need for multiple photolithography and etching processes, which require expensive photo-masks and increase costs with larger panel sizes.
Innovation Solution
A method using laser ablation to form the gate and simultaneously create the channel layer, source, and drain, reducing the number of photolithography and etching processes, and employing shadow masks instead of high-precision photo-masks to simplify the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithography and etching processes are used to fabricate pixel structures, then manufacturing precision is improved, but fabrication cost increases
Solution Approach 1:
The patent combines multiple photolithography and etching processes into a single integrated process. Specifically, it merges the formation of gate, channel layer, source, and drain into one simultaneous fabrication step, eliminating the need for separate process steps and expensive photo-masks while maintaining manufacturing precision.
Solution Approach 2:
The invention employs a universal fabrication approach where a single process step performs multiple functions: forming the gate, channel layer, source, and drain simultaneously. This multi-functional process replaces multiple specialized photolithography and etching steps, reducing overall fabrication cost while maintaining precision.
2Manufacturing precision
If photo-masks are used for each photolithography process, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple photo-mask requirements into a single process without traditional photo-masks. The simultaneous formation of gate, channel layer, source, and drain in one step eliminates the need for multiple patterned photo-masks, reducing device complexity while maintaining pattern formation precision through the unified process design.
3Manufacturing precision
If conventional photolithography processes are used, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent combines multiple sequential photolithography and etching operations into a single simultaneous fabrication process. This merging of processes maintains feature dimension control through precise process integration while dramatically improving fabrication throughput by eliminating repeated process cycles.
Solution Approach 2:
The invention performs preliminary preparation of all layer structures (gate, channel, source, drain) in advance through a single unified process step, rather than forming them sequentially. This preliminary action enables simultaneous creation of all components, maintaining precision while accelerating production speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases the fabrication cost by reducing the number of process steps and eliminating the need for complex photolithography, while maintaining the quality of the pixel structure, and allows for the repair of defects such as ITO or IZO residues, thereby enhancing production yield.
Implementation Method 1
laser is able to pass through the first shadow mask to irradiate the first conductive layer, so that the exposed part of the first conductive layer can be removed to form a gate
Data Source
AI summary
A method for fabricating a pixel structure includes following steps. First, a substrate is provided. Next, a first conductive layer is formed on the substrate. Next, a first shadow mask is disposed over the first conductive layer. Next, a laser is applied through the first shadow mask to irradiate the first conductive layer to form a gate. Next, a gate dielectric layer is formed on the substrate to cover the gate. After that, a channel layer, a source and a drain are simultaneously formed on the gate dielectric layer over the gate, wherein the gate, the channel layer, the source and the drain together form a thin film transistor. A patterned passivation layer is formed on the thin film transistor and the patterned passivation layer exposes a part of the drain. Furthermore, a pixel electrode electrically connecting to the drain is formed.