Thin Film Transistor Substrate with Segmented Gate Dielectric
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Solution Overview
Problem
Conventional thin film transistor substrates face a challenge in simultaneously reducing the driving current and capacitance between the data line and the gate line, as thinner gate dielectric layers decrease driving current but increase capacitance.
Innovation Solution
The proposed solution involves a thin film transistor substrate structure with a planarization layer and a first insulation layer disposed between the data line and the gate line, which includes a gate electrode, a source electrode, and a drain electrode, allowing for reduced capacitance while maintaining efficient driving current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the gate dielectric layer thickness is reduced to reduce driving current, then the driving current of the thin film transistor is reduced, but the capacitance between the data line and the gate line increases
Solution Approach 1:
The gate dielectric layer is segmented into a first gate dielectric layer and a second gate dielectric layer with different thicknesses. The first gate dielectric layer has a greater thickness than the second gate dielectric layer, allowing the capacitance between the data line and gate line to be reduced while maintaining sufficient insulation to control driving current.
Solution Approach 2:
Different regions of the gate dielectric layer have different thicknesses to serve different functions. The first gate dielectric layer (thicker) provides sufficient insulation to control driving current, while the second gate dielectric layer (thinner) reduces capacitance in the overlapping region between data line and gate line.
Data Source
AI summary
A display panel is provided, which includes a substrate and a first metal layer on the substrate. The first metal layer includes a gate electrode and a gate line connecting to the gate electrode. A first insulation layer is disposed on the first metal layer. A planarization layer is disposed on the first insulation layer. An opening, overlapping the gate electrode, is defined by sidewalls of the planarization layer and a surface of the first insulation layer. An active layer is disposed on the opening and the planarization layer. A second metal layer is disposed on the semiconductor layer, and includes a source electrode contacting the active layer and a data line connecting to the source electrode. The planarization layer and the first insulation layer are disposed between the data line and the gate line.