Thin Film Transistor Substrate Cooling for RC Delay

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Solution Overview

Problem

As display apparatuses increase in size, the electrical resistance of signal lines in thin film transistor substrates increases, leading to RC signal delay, which can be mitigated by forming signal lines with a low-resistance metal of increased thickness, but this prolongs the deposition process and may cause substrate deformation due to high temperatures.

Innovation Solution

A method and apparatus for manufacturing thin film transistor substrates that involve forming metal layers on a base substrate, cooling the substrate using opposing cooling plates to maintain a temperature between -60°C to 0°C, and preheating before patterning to prevent deformation, utilizing conductive materials like Au, Cu, Ni, Al, Mo, Cr, Ta, and their alloys, and transparent conductive materials like ITO, IZO, and AZO.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the signal lines are formed with increased thickness to reduce electrical resistance, then the RC signal delay is reduced, but the deposition process time increases and substrate deformation occurs due to high temperature

Engineering Contradiction:
ImproveRC signal delayVSAvoiddeposition process time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the temperature parameter during deposition by introducing a cooling system that maintains the substrate at a reduced temperature (e.g., using liquid nitrogen or cold plates). This parameter change allows for faster deposition rates without causing substrate deformation, thus resolving the contradiction between reducing RC delay through thicker lines and minimizing deposition time while preventing thermal damage

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the signal lines are formed with increased thickness to reduce electrical resistance, then the RC signal delay is reduced, but the substrate temperature rises causing deformation

Engineering Contradiction:
ImproveRC signal delayVSAvoidsubstrate temperature
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent introduces a cooling intermediary system (such as cold plates, liquid nitrogen circulation, or cryogenic cooling layers) between the substrate and the deposition environment. This intermediary actively removes heat during the deposition process, allowing thicker signal lines to be formed without causing substrate temperature rise and deformation, thus resolving the contradiction between reducing RC delay and controlling substrate temperature

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents substrate deformation and reduces RC signal delay by efficiently forming thin film transistor substrates with controlled temperature management and material selection, enhancing the quality and performance of display apparatuses.

Implementation Method 1

the base substrate is cooled by contacting the first metal layer with a first cooling plate and by contacting a second surface of the base substrate with a second cooling plate

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

a first metal layer is formed on a first surface of a base substrate

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS9748283B2System and method of manufacturing a thin film transistor substrate
Publication Date: 2017.08.29 SAMSUNG DISPLAY CO LTD
  • US9748283B2 patent drawing
  • US9748283B2 patent drawing
  • US9748283B2 patent drawing

AI summary

In a method of manufacturing a thin film transistor substrate, a first metal layer is formed on a first surface of a base substrate. The base substrate is cooled by contacting the first metal layer with a first cooling plate and by contacting a second surface of the base substrate with a second cooling plate. The first and second surfaces of the base substrate face opposite directions. A gate electrode is formed by patterning the first metal layer. A source electrode and a drain electrode are formed. The source electrode is spaced apart from the drain electrode. The source and drain electrodes partially overlap the gate electrode. A pixel electrode electrically connected to the drain electrode is formed.