TFT Substrate Mask Reduction via Gate Self-Alignment
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Solution Overview
Problem
The existing manufacturing process for TFT substrates is complex, verbose, and costly due to the requirement of multiple masks and extensive photolithography processes, leading to lower production efficiency and yield.
Innovation Solution
A simplified method involving the use of the gate as a mask for backside exposure and gray scal exposure to form island-shaped layers, reducing the number of masks needed and streamlining the process, while employing self-alignment techniques to enhance precision and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithography processes with separate masks are used for each layer structure, then each layer can be formed with precise control, but the manufacturing process becomes verbose, complex, and time-consuming, reducing production efficiency and increasing costs
Solution Approach 1:
The patent merges multiple photolithography processes into a single integrated process. Specifically, it combines the formation of the semiconductor layer pattern and the insulating layer pattern into one photolithography step, where a single photoresistor layer is used to define both patterns simultaneously. This merging eliminates the need for multiple separate masks and processing steps, thereby maintaining manufacturing precision while significantly improving productivity and reducing costs.
Solution Approach 2:
The single photoresistor layer serves multiple functions: it defines the pattern for the semiconductor layer, defines the pattern for the insulating layer, and acts as a mask for both etching processes. This multi-functionality allows one photolithography process to accomplish what traditionally required multiple separate processes, reducing complexity and increasing production efficiency without sacrificing precision.
2Manufacturing precision
If multiple masks are required for each photolithography process, then each layer pattern can be accurately defined, but the manufacturing cost increases and the number of processes accumulates, leading to significant yield issues
Solution Approach 1:
The patent combines multiple mask functions into a single mask (the photoresistor layer). Instead of using separate masks for the semiconductor layer pattern and the insulating layer pattern, the invention uses one photoresistor layer that is patterned to define both features simultaneously. This merging reduces the number of masks from multiple to one, simplifying the device complexity while maintaining pattern definition accuracy through careful photoresistor design.
Solution Approach 2:
The photoresistor layer is segmented into different functional regions: one region serves as the mask for semiconductor layer formation, while another region serves as the mask for insulating layer formation. This segmentation within a single layer allows the patent to achieve the pattern definition accuracy of multiple masks while reducing the overall number of masks to just one, thereby reducing device complexity and process accumulation.
3Manufacturing precision
If traditional multi-step photolithography processes are used, then each layer can be formed with proper alignment, but the process time increases and manufacturing cost rises, affecting overall yield
Solution Approach 1:
The patent merges multiple alignment operations into a single alignment step. By using one photoresistor layer to define both the semiconductor layer pattern and the insulating layer pattern, the invention eliminates the need for multiple alignment operations between separate photolithography processes. This single alignment operation maintains precision while significantly reducing the time lost to repeated alignment procedures, thereby improving overall yield.
Solution Approach 2:
The photoresistor layer is prepared in advance with the complete pattern information for both the semiconductor layer and the insulating layer. This preliminary action of defining both patterns in a single photoresistor layer before any etching or deposition occurs allows subsequent processes to proceed without repeated alignment steps, reducing process time while maintaining alignment precision through the pre-established pattern.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the number of masks required, shortens the manufacturing process, lowers costs, and increases yield, while improving alignment precision and luminous efficiency.
Implementation Method 1
employing the gate as a mask to implement a back side expose to the first photoresistor layer to form an island shaped first photoresistor layer directly over the gate
Implementation Method 2
etching the oxide semiconductor layer according to a pattern of the island shaped first photoresistor layer to form an island shaped oxide semiconductor layer
Data Source
AI summary
The present invention provides a manufacture method of a TFT substrate, and the method comprises steps of: step 1, forming a gate (21) on a substrate (1); step 2, deposing a gate isolation layer (3); step 3, deposing an oxide semiconductor layer (4) and a first photoresistor layer (5); step 4, taking the gate (21) as a mask to implement a back side expose to the first photoresistor layer (5); step 5, forming an island shaped oxide semiconductor layer (41), and removing the island shaped first photoresistor layer (51); step 6, forming an island shaped etching stopper layer (6); step 7, forming a source/a drain; step 8, deposing a protecting layer (8), a second photoresistor layer (9), and implementing gray scal exposure, development to the second photoresistor layer (9); step 9, forming a pixel electrode via (81) to implement ashing process to the second photoresistor layer (9); step 10, deposing a pixel electrode layer (10); step 11, removing the remaining second photoresistor layer (9′), and forming a pixel electrode (10′); step 12, implementing anneal process.