TFT Substrate Etching via Segmented Gate and Dielectric Vias
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Solution Overview
Problem
The existing TFT substrate manufacturing methods face challenges in controlling the etching process of interlayer dielectric and gate insulation layers, leading to non-penetrating or over-etching vias, which damages the active layer and results in product defects due to higher etching thickness.
Innovation Solution
The method involves forming ion heavily doped areas on the active layer, using a photo-resist layer to create specific vias and through-holes, and performing separate dry etching on the gate insulation and interlayer dielectric layers to form bridging metal blocks and source/drain contacts, improving control and reducing process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If simultaneous etching is performed on the interlayer dielectric layer and gate insulation layer to form vias, then the manufacturing process is simplified, but the etching control becomes difficult leading to non-penetrating vias or over-etching damage
Solution Approach 1:
The patent divides the simultaneous etching process into two separate sequential etching steps: first etching the gate insulation layer to form through-holes, then etching the interlayer dielectric layer to form vias. This segmentation allows independent control of each etching process, preventing the control difficulties and precision losses associated with simultaneous etching of multiple layers.
2Strength
If the total thickness of interlayer dielectric layer and gate insulation layer is increased, then the device structure is more robust, but the etching process becomes harder to control and stops prematurely
Solution Approach 1:
By segmenting the etching process into two separate steps targeting different layers, the patent enables each etching operation to handle a reduced thickness individually. The first etching step processes only the gate insulation layer, and the second step processes only the interlayer dielectric layer, thereby maintaining etching control precision even when the total combined thickness is large.
3Reliability
If over-etching is performed to ensure via penetration, then complete via formation is achieved, but the active layer is damaged resulting in product defects
Solution Approach 1:
The patent segments the etching process so that the first etching step forms through-holes through the gate insulation layer only, and the second etching step forms vias through the interlayer dielectric layer down to the metal layer. This segmentation ensures each etching step stops at the intended target layer without penetrating into the active layer, thereby eliminating over-etching damage while maintaining reliable via formation.
Solution Approach 2:
The patent performs preliminary etching of the gate insulation layer to form through-holes before etching the interlayer dielectric layer. This preliminary action creates a controlled pathway that guides subsequent etching and prevents uncontrolled penetration into the active layer, thereby protecting the active layer from damage while ensuring complete via formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances active layer uniformity, reduces process difficulty, and prevents etching issues caused by higher etching thickness, resulting in improved product quality by allowing precise control over the etching process and minimizing damage to the active layer.
Implementation Method 1
performing etching and exposure with a half tone mask on the photo-resist layer to form a first groove and two first vias on the photo-resist layer
Implementation Method 2
performing etching and exposure with a half tone mask on the photo-resist layer
Implementation Method 3
performing etching on the gate insulation layer to form two first through-holes
Implementation Method 4
performing ion doping at two ends of the active layer to form two ion heavily doped areas
Implementation Method 5
depositing a first metal layer on the gate insulation layer, performing patternizing on the first metal layer to obtain a gate
Data Source
AI summary
The invention provides a TFT substrate manufacturing method and TFT substrate. The TFT substrate manufacturing method first etches the gate insulation layer to form two first through-holes and forming two bridging metal blocks inside the two first through holes; then etches the interlayer dielectric layer to form two second through-holes connecting respectively the two first through-holes, the source and drain connecting the two bridging metal blocks respectively through the two second through-holes. By changing a conventional etching process into two etching process to form the through-hole structure on the gate insulation layer and interlayer dielectric layer, able to improve uniformity of the active layer, reduce process difficulty, avoid the problem of etching stopped due to higher etching thickness, and improve the product quality.