TFT Array Substrate Via Hole Alignment via Photolithography Mask
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Solution Overview
Problem
Display devices with TFT array substrates often experience a 'trace mura' phenomenon, which degrades display quality and affects the display effect due to misalignment issues between via holes in the transparent conductive layers and organic layers, leading to short circuits and defective pixels.
Innovation Solution
A method of manufacturing a TFT array substrate involving the formation of aligned via holes using a photolithography layer as a mask, ensuring precise alignment and avoiding oversize overlapping, which includes forming a first transparent conductive layer, an organic layer, and an insulation layer with specific via holes to prevent short circuits and improve electrostatic shielding, thereby reducing power consumption and enhancing display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If via holes in transparent conductive layers and organic layers are formed without precise alignment, then manufacturing process is simpler, but short circuits and defective pixels occur leading to trace mura phenomenon
Solution Approach 1:
A photolithography layer is introduced as an intermediary mask layer to enable precise alignment of via holes across multiple layers. This mask layer serves as a common reference for patterning both the organic layer and the first transparent conductive layer, ensuring accurate alignment without increasing overall process complexity
Solution Approach 2:
The photolithography layer is formed and patterned in advance before forming the via holes in the organic layer and transparent conductive layer. This preliminary patterning establishes the alignment reference that guides subsequent via hole formation, ensuring precise alignment is achieved systematically
2Manufacturing precision
If via holes are made oversized to ensure alignment, then alignment tolerance is improved, but overlapping area increases causing short circuits
Solution Approach 1:
The photolithography mask layer acts as an intermediary that defines precise via hole patterns, allowing minimal overlap between conductive layer via holes and organic layer via holes. This eliminates the need for oversized via holes while maintaining alignment tolerance through the mask's precise patterning
Solution Approach 2:
Different layers have different via hole characteristics optimized for their specific functions: the photolithography mask provides precise alignment patterns, the organic layer via holes are sized appropriately for TFT formation, and the transparent conductive layer via holes are precisely aligned to both. Each layer's via holes have locally optimized dimensions rather than uniform oversized holes
3Ease of manufacture
If misalignment between via holes occurs, then manufacturing is easier, but display quality degrades due to trace mura phenomenon
Solution Approach 1:
The photolithography mask layer serves as a common intermediary reference for patterning both the organic layer and transparent conductive layer via holes. This single mask ensures consistent alignment patterns across layers, maintaining display quality while simplifying the manufacturing process through a unified alignment approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively prevents short circuits and defective pixels, improves display quality, reduces power consumption, and avoids the trace mura phenomenon by ensuring precise alignment and appropriate sizing of via holes, thus enhancing the yield and aperture ratio of the display panel.
Implementation Method 1
forming a photolithography layer on the first transparent conductive layer, where the photolithography layer has an opening. The method also includes patterning the first transparent conductive layer to form a first via hole in the first transparent layer using the photolithography layer as a mask
Data Source
AI summary
A TFT substrate and a method of manufacturing the TFT array substrate are disclosed. The method includes providing a substrate, forming an organic layer on the substrate, forming a first transparent conductive layer on the organic layer, and forming a photolithography layer on the first transparent conductive layer, where the photolithography layer has an opening. The method also includes patterning the first transparent conductive layer to form a first via hole in the first transparent layer using the photolithography layer as a mask, where the first via hole is aligned with the opening in the photolithography layer, and patterning the organic layer to form a second via hole in the organic using the photolithography layer as a mask, where the second via hole is aligned with the opening in the photolithography layer.