TFT-LCD Pixel Unit Three-Mask Photolithography Process
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Solution Overview
Problem
Conventional TFT-LCD manufacturing processes require strict process tolerance and multiple masks, leading to increased costs, machine occupation time, and reduced yield.
Innovation Solution
A TFT-LCD pixel unit is manufactured using a three-mask photolithography process, with a gate line and gate electrode formed on a substrate, followed by sequential deposition of a first gate insulating layer, active layer, and doped layer, and then a second insulating layer, reducing the complexity and tolerance requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a four-mask method is used to etch source/drain metal layer and active layer, then etching precision can be improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the etching of source/drain metal layer and active layer into a single etching process step, eliminating the need for separate etching steps required in conventional four-mask methods. This merging of operations reduces process complexity while maintaining etching precision through the use of a specially designed gray tone mask that provides appropriate exposure patterns for both layers simultaneously.
Solution Approach 2:
The gray tone mask serves multiple functions: it defines the pattern for source/drain metal layer etching, defines the pattern for active layer etching, and controls the exposure of different regions (channel portion vs. non-channel portions) all in a single masking operation. This multi-functionality eliminates the need for multiple separate masks and processes.
2Manufacturing precision
If a four-mask method is used with strict process control, then etching uniformity can be improved, but machine occupation time increases
Solution Approach 1:
The patent merges multiple etching operations into a single process step, reducing the total machine occupation time. The gray tone mask is designed to enable simultaneous etching of source/drain metal layer and active layer with uniformity, eliminating the need for multiple sequential masking and etching operations that would increase production time.
3Manufacturing precision
If gray tone mask is used to etch channel portion, then pattern definition can be improved, but process tolerance requirements increase
Solution Approach 1:
The gray tone mask employs local quality by having different optical densities in different regions: the channel portion region has a specific gray tone that allows partial exposure for precise pattern definition, while non-channel portions have different exposure characteristics. This spatial variation in mask properties enables precise pattern definition while reducing sensitivity to process variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the cost of the array process, shortens machine occupation time, and increases yield while simplifying the design and improving process tolerance, and allows for the integration of the data line and source/drain electrodes with the pixel electrode, thus addressing the limitations of conventional methods.
Implementation Method 1
a TFT is formed by a photolithography process using three masks
Implementation Method 2
a gate metal layer is formed by a conventional gate process, and then a gate insulating layer is deposited
Implementation Method 3
a semiconductor active layer, a doped layer, and a source/drain metal layer are deposited
Data Source
AI summary
A thin film transistor liquid crystal display (TFT-LCD) pixel unit and a method for manufacturing the same. The pixel unit comprises a gate line and a gate electrode formed on a substrate and a first gate insulating layer, an active layer, and a doped layer that are sequentially formed on the gate line and the gate electrode. An intercepting trench is formed on the gate line to cut off the doped layer and the active layer on the gate line. A second insulating layer covers the intercepting trench and the substrate where the gate line and the gate electrode are not formed. A pixel electrode is formed on the second insulating layer and a part of the pixel electrode overlaps one of a source and drain electrodes.