Thermal Gradient Detection in Stacked Semiconductor Devices
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Solution Overview
Problem
Semiconductor devices experience unexpected thermal gradients due to mechanical coupling, leading to operating errors such as inappropriate refresh frequencies and data loss in DRAM, as existing thermal sensing methods may not accurately account for non-uniform thermal distributions between closely packed devices.
Innovation Solution
Standardizing the location of thermal sensors across all devices in a stack and using a SoC or computational element to calculate temperature differences between standardized locations and hotspots, allowing DRAM to adjust refresh rates based on accurate thermal information, or calculating maximum temperature gradients to ensure data integrity at the cost of increased power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thermal sensors are placed at standardized locations across all devices in a stack, then ease of manufacture and device consistency are improved, but measurement precision of local hotspots deteriorates
Solution Approach 1:
The system divides the temperature measurement task into two segments: a standardized thermal sensor at a fixed location for consistent manufacturing, and a computational element (SoC) that calculates the temperature difference between the standardized location and the hotspot. This segmentation allows standardized placement while still obtaining accurate hotspot temperature information through computational adjustment.
Solution Approach 2:
The patent introduces an intermediary computational element (the SoC or other computational device) that acts as a mediator between the standardized thermal sensor and the required hotspot temperature information. The computational element calculates the temperature difference and uses this to adjust the standardized sensor reading, thereby obtaining accurate hotspot temperature without placing a sensor directly at the hotspot.
2Reliability
If refresh rates are adjusted based on accurate thermal information, then data integrity is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the DRAM refresh rate based on the calculated temperature difference between the standardized sensor location and the hotspot. Instead of using a fixed refresh rate, the refresh rate is adapted in real-time according to the actual thermal conditions, ensuring data integrity when temperatures are high while reducing power consumption when temperatures are lower.
Solution Approach 2:
The patent changes the operational parameter (refresh rate) of the DRAM based on thermal conditions. By calculating the temperature difference and using this information to adjust the refresh rate, the system optimizes the balance between data integrity and power consumption, only increasing refresh rates when thermal conditions require it.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates data loss by ensuring accurate thermal monitoring and adjusting refresh rates, thereby maintaining data integrity while managing power consumption in semiconductor devices with varying thermal gradients.
Implementation Method 1
a thermal sensor may be placed in a standardized location on a memory module die... The standardized location may be offset from a vertical interconnect array... Temperature information may be used to adjust an operation of the memory module
Implementation Method 2
Because the thermal energy may not be uniform, a thermal gradient may exist. As systems become smaller and semiconductor devices are more closely packed, which may result in mechanical coupling between devices. This tight mechanical coupling may result in unexpected induced thermal gradients between one and another of the semiconductor devices
Data Source
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AI summary
An apparatus comprising: a semiconductor die including: a first thermal sensor and a second thermal sensor, the first and second thermal sensors to detect a thermal gradient, and logic circuitry to provide a thermal offset bit to a storage location for the thermal offset bit of a mode register of a memory die responsive to detection of a change in the thermal gradient, the memory die including dynamic random access memory (DRAM); wherein the thermal offset bit is to direct a temperature compensated self-refresh (TCSR) logic of the memory die to modify a self-refresh rate of the DRAM; wherein the first thermal sensor is to be aligned with or in close proximity with a memory thermal sensor of the memory die, and wherein the second thermal sensor of the semiconductor die is located at a hot spot of the semiconductor die.