Thermal Interface Material Layer for Package-on-Package Crack Prevention
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Solution Overview
Problem
Package-on-package devices face challenges with heat dissipation and mechanical stress, leading to device malfunctions and reduced operation speed due to the large thickness and difficulty in exhausting heat from semiconductor chips, which can cause cracking during the solder ball joint process.
Innovation Solution
A thermal interface material layer with a modulus of elasticity of 500 kPa or less and Mohs hardness lower than 7 is interposed between the lower and upper semiconductor packages, composed of a resin layer and filler particles, such as boron nitride or zinc oxide, to absorb impact and enhance heat transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a package-on-package structure is used to achieve compact electronic systems, then the device thickness increases, but heat dissipation becomes difficult and device reliability deteriorates
Solution Approach 1:
A thermal interface material layer is introduced as an intermediary between the lower semiconductor chip and upper package substrate. This layer has specialized properties (modulus of elasticity ≤500 kPa, Mohs hardness <7, thermal conductivity ≥1 W/mK) that enable it to mediate both mechanical stress absorption and thermal conduction, resolving the contradiction between compact structure and heat dissipation capability
Solution Approach 2:
The patent changes the physical parameters of the interface layer by selecting materials with specific modulus of elasticity (≤500 kPa) and Mohs hardness (<7) values. This parameter optimization allows the layer to deform under stress, preventing crack propagation while maintaining thermal contact, thus improving reliability in the compact PoP structure
2Productivity
If the upper semiconductor package is mounted on the lower semiconductor package, then device integration is achieved, but mechanical stress causes cracking in the lower chip
Solution Approach 1:
The thermal interface material layer is placed beforehand between the lower chip and upper package substrate to provide cushioning against mechanical stress. Its low modulus of elasticity (≤500 kPa) and low Mohs hardness (<7) enable it to absorb impact forces during mounting, preventing cracks in the lower semiconductor chip while maintaining device integration
3Stability of the object's composition
If a rigid thermal interface material is used to maintain structural stability, then mechanical strength is improved, but thermal conductivity and crack resistance deteriorate
Solution Approach 1:
The patent optimizes material parameters by selecting thermal interface materials with modulus of elasticity ≤500 kPa and Mohs hardness <7. These parameter changes create a soft yet thermally conductive layer that maintains structural stability through controlled deformation while preventing cracks and ensuring efficient heat transfer
Solution Approach 2:
The thermal interface material layer is composed of resin-based compounds (silicon or rubber) potentially combined with filler particles. This composite structure provides both the mechanical softness needed for crack resistance and the thermal conductivity required for heat dissipation, resolving the contradiction between structural stability and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The thermal interface material layer prevents cracking of the lower semiconductor chip, improves the yield and operation speed of the package-on-package device by effectively dissipating heat and reducing the risk of malfunction.
Implementation Method 1
The thermal interface material layer has thermal conductivity of 1 W/mK or higher
Implementation Method 2
the thermal interface material layer has modulus of elasticity of 500 kPa or less
Data Source
AI summary
Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.