Thermally Stable Charge Trapping Layer for SOI RF Devices
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Solution Overview
Problem
Conventional charge trapping layers in semiconductor-on-insulator wafers lose effectiveness due to thermal processing, leading to reduced resistivity and performance issues in RF devices.
Innovation Solution
A method is developed to create a thermally stable charge trapping layer by etching a porous layer on a single crystal semiconductor handle substrate, oxidizing the pores, and filling them with amorphous or polycrystalline semiconductor material, which maintains charge trapping efficiency even under high-temperature processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional charge trapping layer is used in semiconductor-on-insulator wafers, then charge trapping is initially effective, but thermal processing causes loss of charge trapping effectiveness and reduced resistivity
Solution Approach 1:
The patent changes the material parameters of the charge trapping layer by using a composite structure with specific materials (e.g., tungsten oxide, molybdenum oxide, or their mixtures with silicon dioxide) and controlled thicknesses. This composite composition maintains charge trapping effectiveness while providing thermal stability during processing, resolving the contradiction between initial effectiveness and thermal stability.
Solution Approach 2:
The patent employs composite materials in the charge trapping layer, combining metal oxides (tungsten oxide, molybdenum oxide) with silicon dioxide in specific ratios. This composite structure provides both the charge trapping functionality and the thermal stability required, as the metal oxides maintain their charge trapping properties while the silicon dioxide matrix provides thermal resistance.
2Ease of manufacture
If thermal processing is applied to semiconductor-on-insulator wafers, then device fabrication is enabled, but charge trapping layer effectiveness is reduced leading to parasitic conductive channel formation
Solution Approach 1:
The patent converts the potential harm of thermal processing into a benefit by designing a charge trapping layer that not only withstands thermal processing but actually benefits from it. The metal oxide-based composite layer maintains or even enhances its charge trapping effectiveness after thermal processing, preventing parasitic conductive channel formation while enabling complete device fabrication.
3Object-affected harmful factors
If high resistivity handle substrate is used for RF devices, then parasitic power loss is reduced, but charge trapping is insufficient without additional layers
Solution Approach 1:
The patent merges the functions of the handle substrate and the charge trapping layer by integrating the charge trapping functionality directly into the handle substrate structure through the composite metal oxide-silicon dioxide layer. This unified structure simultaneously provides high resistivity to reduce parasitic power loss and effective charge trapping to prevent conductive channel formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method produces a thermally stable charge trapping layer that preserves charge trapping effectiveness, reducing parasitic effects and enhancing the performance of RF devices by preventing conductive channel formation below the buried oxide.
Implementation Method 1
the etched surface is exposed to an ambient atmosphere comprising oxygen wherein the exposed, etched surface of the porous film is oxidized
Implementation Method 2
bonding by van der Waal's forces
Data Source
AI summary
A single crystal semiconductor handle substrate for use in the manufacture of semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure is etched to form a porous layer in the front surface region of the wafer. The etched region is oxidized and then filled with a semiconductor material, which may be polycrystalline or amorphous. The surface is polished to render it bondable to a semiconductor donor substrate. Layer transfer is performed over the polished surface thus creating semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure having 4 layers: the handle substrate, the composite layer comprising filled pores, a dielectric layer (e.g., buried oxide), and a device layer. The structure can be used as initial substrate in fabricating radiofrequency chips. The resulting chips have suppressed parasitic effects, particularly, no induced conductive channel below the buried oxide.