Thick Conductive Pads for 3D Semiconductor Contact Landing

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Solution Overview

Problem

The challenge in manufacturing 3D stacked semiconductor structures is the difficulty in forming reliable contact landing on thin polysilicon channels, which affects the electrical performance of the devices.

Innovation Solution

The method involves forming thicker conductive pads using a selective epitaxial growth process on the polysilicon channel layer, ensuring the pads are thicker than the channel layer, thereby enhancing contact landing reliability without damaging related layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If thin polysilicon channel is used, then device performance is improved, but manufacturing difficulty increases

Engineering Contradiction:

Improvedevice performanceVSAvoidcontact landing formation

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The invention applies preliminary action by forming the thin polysilicon channel layer first with precise thickness control for optimal device performance, then subsequently forming the thick conductive pad layer on top. This sequential approach allows the manufacturing process to first establish the performance-critical thin channel, then add the manufacturing-friendly thick pad that facilitates reliable contact landing, thereby improving ease of manufacture without compromising device performance.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the electrical performance reliability of 3D stacked semiconductor structures by providing thicker conductive pads for contact landing, suitable for multiple stacking layers without affecting the structure's configuration, and is suitable for mass production.

Implementation Method 1

a charge trapping layer formed on the patterned multi-layered stacks and deposited in the channel holes as liners

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Implementation Method 2

a polysilicon channel layer deposited along the charge trapping layer

Methodology Applied

Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS10312256B1Method of manufacturing three-dimensional stacked semiconductor structure and structure manufactured by the same

Publication Date: 2019.06.04 MACRONIX INTERNATIONAL CO LTD

AI summary

A three-dimensional (3D) stacked semiconductor structure is provided. A substrate having an array area and a peripheral area is provided, and several patterned multi-layered stacks above the substrate are formed in the array area. The patterned multi-layered stacks are spaced apart from each other, and channel holes are formed between the patterned multi-layered stacks disposed adjacently. A charge trapping layer is formed on the patterned multi-layered stacks and deposited in the channel holes as liners. A polysilicon channel layer is deposited along the charge trapping layer, and conductive pads are formed on the polysilicon channel layer and respectively corresponding to the patterned multi-layered stacks. The polysilicon channel layer has a first thickness (t1), one of the conductive pads has a second thickness (t2), wherein the second thickness (t2) is larger than the first thickness (t1).