Thick Gate Insulation Layer for High-Voltage SOI Transistors
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Solution Overview
Problem
Integrating high-voltage and high-performance transistor devices on the same die is challenging due to differences in dimensional scaling and the need for optimized gate insulation layers, which complicates the manufacturing process and limits the operation voltage of integrated circuits.
Innovation Solution
A semiconductor device with a thick gate insulation layer formed using a buried insulation layer and additional oxide material, allowing for high-voltage operation beyond 10 V, is integrated within the process flow of low-voltage bulk transistor devices and SOI FETs, enabling the formation of high-voltage FETs on the same SOI substrate as low-voltage devices without additional complex patterning procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thin gate insulation layer is used, then high-performance low-voltage transistor operation is achieved, but high-voltage operation capability is limited
Solution Approach 1:
The patent applies local quality by providing different gate insulation layer thicknesses in different regions of the semiconductor device. Specifically, a first gate insulation layer with a first thickness is provided for high-voltage transistor devices, while a second gate insulation layer with a second thickness is provided for low-voltage transistor devices. This allows each region to be optimized for its specific voltage requirement, enabling both high-voltage operation capability and high-performance transistor operation simultaneously.
2Adaptability or versatility
If different gate insulation layer thicknesses are used for high-voltage and low-voltage devices, then both device types can operate at their optimal voltages, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the gate insulation structure into distinct regions with different thicknesses. A first gate insulation layer is formed over a first region of the semiconductor substrate, and a second gate insulation layer is formed over a second region. This segmentation allows independent optimization of gate insulation thickness for high-voltage and low-voltage device regions, supporting multi-voltage operation while managing manufacturing complexity through systematic regional differentiation.
3Reliability
If thicker gate insulation layers are formed during gate patterning of low-voltage FETs, then high-voltage transistor devices can be created, but the overall patterning process is significantly complicated
Solution Approach 1:
The patent applies preliminary action by forming the first gate insulation layer with the greater thickness before forming the second gate insulation layer with the smaller thickness. This sequence allows the thick gate insulation layer to be established in advance for high-voltage device regions, enabling high-voltage transistor operation to be achieved without complicating the subsequent patterning processes for low-voltage devices. The preliminary formation of the thick layer simplifies the overall manufacturing workflow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the successful integration of high-voltage FETs with operation voltages exceeding 10 V, enhancing manufacturing efficiency and reducing complexity by using a thick gate insulation layer that supports both high-voltage and low-voltage devices on the same substrate, facilitating high-yield semiconductor production.
Implementation Method 1
a first gate insulation layer formed above the first channel region, the first gate insulation layer including a part of the buried insulation layer and an oxidized part of the semiconductor layer
Data Source
AI summary
One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.