Patterned Thick Metallization for Power Semiconductor Chips

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Solution Overview

Problem

The challenge in fabricating power semiconductor chips is to achieve reliable copper wire bonding with thick metallization while maintaining alignment accuracy and semiconductor area efficiency, as traditional methods face issues with metal hardness and alignment mark degradation due to increased thickness requirements.

Innovation Solution

A method involving the sequential deposition of a hot metal layer and a cold metal layer atop a semiconductor chip, forming a composite thick metallization with specific thickness ratios and processes to enhance step coverage and alignment accuracy, using compositions like (Al, Si, Cu) for the hot metal and (Al, Cu) for the cold metal, with built-in alignment marks for patterning.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If hot metal process is used to deposit thick metallization, then metal step coverage is improved, but alignment mark sharpness degrades

Engineering Contradiction:
Improvemetal step coverageVSAvoidalignment mark sharpness
Core Design Contradiction:
Manufacturing precisionVSMeasurement precision

Solution Approach 1:

The patent divides the single thick metal layer into two separate deposition processes: a hot metal process for the bottom layer (providing step coverage) and a cold metal process for the top layer (providing sharp alignment marks). This segmentation allows each process to optimize for its specific function without compromising the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the metallization structure are given different properties: the bottom layer uses hot metal deposition to achieve good step coverage in contact holes, while the top layer uses cold metal deposition to maintain sharp alignment marks for subsequent masking processes. Each layer is optimized for its local function.

Inventive Principle:
Principle #3Local quality

2Reliability

If metal layer thickness is increased to accommodate copper wire bonding, then wire bonding reliability is improved, but semiconductor area usage efficiency decreases

Engineering Contradiction:
Improvewire bonding reliabilityVSAvoidsemiconductor area usage efficiency
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the deposition parameters (temperature) to create a composite metal structure that achieves the required thickness for reliable copper wire bonding while optimizing the area usage. The two-layer structure with controlled thicknesses allows meeting both requirements.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If single hot metal layer is used, then metal step coverage is improved, but alignment error rate increases

Engineering Contradiction:
Improvemetal step coverageVSAvoidalignment error rate
Core Design Contradiction:
Manufacturing precisionVSMeasurement precision

Solution Approach 1:

The patent segments the metallization into two layers deposited by different processes. The hot metal process deposits the bottom layer with good step coverage, while the cold metal process deposits the top layer with sharp alignment marks, thereby reducing alignment error rates.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates a composite metallization structure combining two different metal deposition processes. The composite structure leverages the advantages of both hot metal (step coverage) and cold metal (alignment mark quality) processes to achieve overall superior performance.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach provides better step coverage and lower alignment errors, maintaining semiconductor area efficiency and enabling reliable copper wire bonding with reduced yield loss, by leveraging the strengths of both hot and cold metal processes in metallization.

Implementation Method 1

deposit a bottom metal layer of sub-thickness TK1 using a hot metal process

Methodology Applied
Scientific EffectVapor deposition: Physical Vapour Deposition

Implementation Method 2

deposit a top metal layer of sub-thickness TK2 using a cold metal process

Methodology Applied
Scientific EffectVapor deposition: Physical Vapour Deposition

Data Source

PatentUS8354334B2Power semiconductor chip with a formed patterned thick metallization atop
Publication Date: 2013.01.15 ALPHA & OMEGA SEMICONDUCTOR INC
  • US8354334B2 patent drawing
  • US8354334B2 patent drawing
  • US8354334B2 patent drawing

AI summary

A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.