Semiconductor Package Structure Balancing Thin Chips and Capacitor Clearance
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Solution Overview
Problem
Semiconductor devices with low-k interlayer insulating films face thermal stress-induced cracks due to differences in thermal expansion coefficients between silicon substrates and wiring substrates, and thinning the semiconductor chip to prevent cracks results in capacitor terminal short-circuiting, compromising device reliability.
Innovation Solution
A semiconductor device design where the semiconductor chip is thinner than the capacitors, with capacitors mounted in notched portions of the lid to prevent short-circuiting and enhance reliability, and an adhesive layer is used to attach the lid to the chip, allowing for stress relief and improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the semiconductor chip is increased to maintain a gap between the metal lid and capacitor, then the electrical insulation is improved, but the mechanical strength against thermal stress is reduced
Solution Approach 1:
Instead of increasing chip thickness in the horizontal plane, the solution utilizes the vertical dimension by positioning the capacitor between the chip and lid. This allows the chip to maintain its optimal thin profile for mechanical strength while the capacitor achieves electrical insulation through its placement in the vertical space, where the lid and chip act as protective boundaries.
2Stress or pressure
If the semiconductor chip is thinned to reduce thermal stress, then the stress on the interlayer insulating film is reduced, but the gap for capacitor insulation is eliminated
Solution Approach 1:
The patent resolves this contradiction by moving the insulation mechanism from the horizontal plane to the vertical dimension. Thinning the chip reduces thermal stress as intended, while the capacitor's placement in the vertical space between the chip and lid provides the necessary insulation gap. The lid and chip together form a sandwich structure that electrically isolates the capacitor terminals without requiring the chip to be thick.
Solution Approach 2:
The metal lid serves as an intermediary element that provides electrical insulation for the capacitor terminals. By positioning the capacitor between the chip and the lid, the lid acts as a protective barrier that prevents short-circuits while allowing the chip to be thin. This intermediary structure enables both stress reduction and electrical insulation to coexist.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the reliability of semiconductor devices by preventing capacitor short-circuiting and reducing stress on the interlayer insulating film, while maintaining high-speed signal transmission capabilities.
Implementation Method 1
a lid bonded to the first back surface of the semiconductor chip via a first adhesive layer
Implementation Method 2
uses a low-k film having low mechanical strength as an interlayer insulating film for separating a plurality of wiring layers provided on a semiconductor substrate. Here, the Low-k film is defined as an insulating film having a relative dielectric constant of 3.7 or less.
Implementation Method 3
thermal stress is applied to the protruding electrodes due to a difference in thermal expansion coefficient between a semiconductor substrate made of silicon and a wiring substrate
Data Source
AI summary
Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.