Thin-Film LED Chip Rear-Side Insulation via Doped Silicon
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Solution Overview
Problem
Existing thin-film light-emitting diode chips face challenges in achieving effective rear-side insulation without electrical connection between the back and front, which is often expensive and difficult to integrate into standard manufacturing processes.
Innovation Solution
An optoelectronic semiconductor chip design featuring a semiconductor layer sequence grown epitaxially without a growth substrate, attached to a conductive carrier using bonding or joining layers, with an insulating separating layer formed by atomic or molecular layer deposition for precise electrical insulation between the connection layers and the carrier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ceramic carrier (e.g. AlN, SiN) or glass carrier is used for rear-side insulation, then electrical separation between front and back is achieved, but manufacturing cost increases and integration into existing manufacturing processes becomes difficult
Solution Approach 1:
The patent replaces expensive ceramic or glass carriers with a standard silicon carrier that can be heavily doped to achieve electrical insulation. This substitution uses a cheaper, more readily available material that integrates seamlessly into existing silicon-based semiconductor manufacturing processes, eliminating the need for specialized carrier materials while maintaining electrical separation functionality
Solution Approach 2:
The patent changes the electrical parameters of the silicon carrier by applying heavy doping (e.g., boron doping at concentrations of 1e19 to 1e21 atoms/cm³) to transform the conductive silicon carrier into an electrically insulating structure. This parameter change allows the same silicon carrier to serve both mechanical support and electrical insulation functions, resolving the contradiction between reliability and ease of manufacture
2Ease of manufacture
If a heavily doped silicon carrier is used for rear-side insulation, then manufacturing cost decreases and process integration improves, but achieving sufficient dielectric strength becomes challenging
Solution Approach 1:
The patent introduces an insulating layer (such as silicon oxide, silicon nitride, or silicon oxynitride) as an intermediary between the heavily doped silicon carrier and the semiconductor structure. This intermediate layer provides the necessary dielectric strength and electrical insulation, compensating for the reduced insulation properties of the heavily doped silicon while maintaining compatibility with standard manufacturing processes
Solution Approach 2:
The patent creates a composite structure combining the heavily doped silicon carrier with an insulating layer. This composite approach leverages the mechanical stability and ease of manufacture of silicon while adding the electrical insulation properties of the insulating layer, thereby achieving both high dielectric strength and manufacturing efficiency
3Ease of manufacture
If standard silicon carrier with heavy doping is used instead of specialized insulating carriers, then ease of manufacture improves, but additional insulating layers may be required
Solution Approach 1:
The patent makes the silicon carrier multi-functional by heavily doping it to simultaneously provide mechanical support, thermal management, and electrical insulation functions. This universality reduces the need for additional specialized components and can simplify the overall layer structure, as the doped silicon carrier itself becomes the insulation element rather than requiring a separate insulating carrier material
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables reliable and cost-effective rear-side insulation of thin-film light-emitting diode chips, improving dielectric strength and processing efficiency while maintaining compatibility with existing manufacturing processes and reducing the need for specialized carrier materials.
Implementation Method 1
The insulating separating layer comprises one or more atomic or molecular monolayers
Implementation Method 2
The insulating separating layer comprises one or more atomic or molecular monolayers
Implementation Method 3
a semiconductor layer sequence which is grown epitaxially
Data Source
Figure 1~2
Figure 3
AI summary
An optoelectronic semiconductor chip (1), in particular in the shape of a thin-film chip, comprises a carrier (5), and a chip front side, a chip rear side (52) and a semiconductor body (2) arranged on the carrier (5) and having a semiconductor layer sequence. The semiconductor layer sequence comprises an active region (20), which is arranged between a first semiconductor layer (21) and a second semiconductor layer (22). Same is used to generate or to receive electromagnetic radiation. The first semiconductor layer (21) is connected to a first contact (41) in an electrically conductive manner, wherein the first contact (41) is formed on the chip front side, in particular next to the active region (20). The second semiconductor layer (22) is connected to the second contact (42) in an electrically conductive manner, and the second contact (42) is likewise formed on the chip front side, in particular next to the active region (20). An electrically insulating separating layer (6) is formed between the electrical connecting layer (31) and the carrier (5) or within the carrier.