Thin Film Resistor Interconnect via Segmented Via Etching
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Solution Overview
Problem
Existing manufacturing processes for semiconductor devices face challenges in connecting thin film resistors without damaging them, as traditional etching methods can destroy the resistor material and are not compatible with the materials used in thin film resistor layers.
Innovation Solution
A method involving the deposition of conductive and insulating layers, with strategically positioned openings (VIAs) that partially overlap the thin film resistor, allowing for electrical connection using the same dry etching process, and filling these openings with conductive material to ensure reliable and non-destructive contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional etching methods are used to create VIAs for connecting thin film resistors, then electrical connection is achieved, but the resistor material is destroyed
Solution Approach 1:
The patent divides the VIA formation process into two separate steps: first creating a through-hole in the dielectric layer, then selectively depositing conductive material only in the VIA region. This segmentation allows the etching to stop before reaching and damaging the resistor material, while still achieving electrical connection through the conductive fill.
Solution Approach 2:
The patent performs preliminary actions by forming the through-hole VIA opening before depositing the conductive material. The opening is created with precise depth control to stop above the resistor layer, and then conductive material is selectively deposited only in this pre-formed opening, preventing contact with and damage to the resistor material.
2Reliability
If the VIA opening is positioned to connect to the thin film resistor, then electrical connection is achieved, but manufacturing precision is compromised due to material sensitivity
Solution Approach 1:
The patent introduces an intermediary conductive layer that fills the VIA opening and makes contact with the thin film resistor. This intermediary layer acts as a buffer that can tolerate slight positioning variations, reducing the stringent precision requirements for VIA placement while ensuring reliable electrical connection.
Solution Approach 2:
The patent applies different properties to different regions: the VIA opening has precise dimensions and positioning, while the conductive fill material provides local electrical connection with tolerance for positioning variations. The localized conductive fill compensates for positioning inaccuracies without affecting the overall precision of the VIA structure.
3Reliability
If multiple processing steps are added to protect resistor material during VIA etching, then resistor integrity is maintained, but device complexity increases
Solution Approach 1:
The patent extracts the potentially harmful etching action from direct contact with the resistor material by creating a through-hole that stops above the resistor layer. The etching process is separated from the resistor interaction, eliminating the need for complex protective measures while maintaining resistor integrity.
Solution Approach 2:
The conductive material deposition process automatically fills the VIA opening and self-limits its contact with the resistor material due to the pre-formed opening geometry. The structure itself provides the protection needed, eliminating the requirement for additional protective processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable electrical connection of thin film resistors with reduced parasitic resistance and increased tolerance for the position of the resistive layer, maintaining the integrity of the resistor material and simplifying the manufacturing process.
Implementation Method 1
A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer.
Implementation Method 2
The openings are filled with conductive material to ensure reliable and non-destructive contact.
Data Source
AI summary
The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is deposited. There is an insulating layer (first intermetal dielectric) layer deposited. A resistive layer is deposited on top of the insulating layer and structured in order to serve as a thin film resistor. A second insulating layer (second intermetal dielectric) is then deposited on top of the resistive layer. A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer. A cross-sectional plane of the second opening is arranged such that it at least partially overlaps the resistive layer of the thin film resistor in a first direction.