Thin Power Device Substrate With Embedded Chip And Vertical Interconnects
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Solution Overview
Problem
Traditional wire bonding and clip bonding methods result in thick semiconductor device packages with poor heat dissipation due to high bonding wire loops and thick pins, making it difficult to achieve thinner devices.
Innovation Solution
A substrate with contact pads on both surfaces and a central opening for embedding a semiconductor chip, using aerosol jet printed conductive strips or bonding wires/metal clips for interconnections, and a thin metal interconnecting structure within trenches or through holes to reduce device thickness and enhance heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding or clip bonding is used for interconnection, then electrical connection is achieved, but the device thickness increases due to high bonding wire loops or deep downset of clips
Solution Approach 1:
The patent transitions from planar bonding methods (wire bonding/clip bonding on the same plane) to a three-dimensional configuration where the interconnection structure extends vertically through the substrate via trenches and through-holes. This dimensional change allows electrical connection while minimizing the horizontal footprint and reducing overall device thickness.
Solution Approach 2:
The interconnection structure is nested within the substrate itself, with conductive paths embedded in trenches or through-holes that pass through the substrate thickness. This nesting approach integrates the interconnection function within the substrate volume rather than adding external bonding elements, thereby reducing device thickness.
2Strength
If traditional bonding methods with thick pins and paddles are used, then mechanical support and electrical connection are provided, but heat dissipation performance deteriorates
Solution Approach 1:
The patent extracts the interconnection function from traditional thick pins and paddles, embedding slim conductive paths directly within the substrate. This separation of functions allows the substrate to provide both mechanical support and thermal management while the embedded conductors provide electrical connection with minimal thermal resistance.
Solution Approach 2:
The substrate employs composite construction combining insulating material with embedded conductive paths (such as metal-filled trenches or through-holes). This composite structure provides mechanical strength, electrical connection, and improved thermal conduction pathways separate from the traditional thick metal pins and paddles.
3Strength
If thick pins and paddles are used for mounting and connection, then mechanical strength is sufficient, but the overall device thickness increases
Solution Approach 1:
The patent moves the interconnection structure into the vertical dimension by creating trenches and through-holes that pass through the substrate thickness. This allows slim conductive paths to achieve mechanical strength through their embedded configuration and distribution rather than relying on thick individual pins or paddles.
Solution Approach 2:
The interconnection function is segmented into multiple distributed conductive paths embedded within the substrate rather than using a few thick pins. This segmentation provides sufficient mechanical strength through distributed support while maintaining thin overall device thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach allows for the creation of thinner power devices with improved heat dissipation capabilities by embedding the chip in the substrate and using thin interconnecting structures, reducing the overall device thickness and enhancing thermal management.
Implementation Method 1
using aerosol jet printed conductive strips or bonding wires/metal clips for interconnections
Data Source
AI summary
A preparation method of a thin power device comprising the steps of steps S1, S2 and S3. In step S1, a substrate is provided. The substrate comprises a first set of first contact pads and a second set of second contact pads arranged at a front surface and a back surface of the substrate respectively. Each first contact pad of the first set of contact pads is electrically connected with a respective second contact pad of the second set of contact pads via a respective interconnecting structure formed inside the substrate. A through opening is formed in the substrate aligning with a third contact pad attached to the back surface of the substrate. The third contact pad is not electrically connected with the first set of contact pads. In step S2, a semiconductor chip is embedded into the through opening. A back metal layer at a back surface of the semiconductor chip is attached to the third contact pad. In step S3, a respective electrode of a plurality of electrodes at a front surface of the semiconductor chip is electrically connected with said each first contact pad of the first set of contact pads via a respective conductive structure of a plurality of conductive structures.