Thin Redistribution Layers for Semiconductor Device Thickness Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional Package On Package (POP) semiconductor devices are thick due to the use of thick printed circuit boards and large solder balls, leading to warping and increased manufacturing costs, and they lack the flexibility to accommodate highly integrated semiconductor dies.
Innovation Solution
The semiconductor device employs thin redistribution layers formed on a dummy substrate, with a multi-layered structure of dielectric and conductive layers, allowing for a significant reduction in thickness and pitch, and eliminating the need for a conventional PCB, thereby enabling the direct connection of semiconductor dies and reducing thermal expansion mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a thick printed circuit board is used as a substrate in conventional POP, then the structural support is sufficient, but the overall thickness becomes 1 mm or greater and warping occurs due to thermal expansion mismatch
Solution Approach 1:
The patent extracts and removes the thick printed circuit board substrate from the POP structure, replacing it with thin redistribution layers formed directly on the dummy substrate. This eliminates the source of thermal expansion mismatch and warping while maintaining necessary structural support through the redistribution layer architecture.
Solution Approach 2:
The patent changes the thickness parameter of the substrate from conventional thick PCB (1 mm or greater) to thin redistribution layers (significantly reduced thickness). This parameter change is achieved through forming multiple thin conductive and dielectric layers directly on the dummy substrate, fundamentally altering the structural composition to eliminate warping issues.
2Reliability
If a thick printed circuit board and large solder balls are used in conventional POP, then reliable electrical connection is achieved, but the manufacturing cost increases and flexibility to accommodate highly integrated dies is lost
Solution Approach 1:
The patent segments the electrical connection function into multiple thin redistribution layers with progressively smaller pitch, replacing the single thick PCB and large solder ball approach. This segmentation allows the structure to accommodate highly integrated semiconductor dies with finer interconnect requirements while maintaining reliable electrical connections through the multi-layer architecture.
Solution Approach 2:
The patent transitions from a two-dimensional connection approach (large solder balls on thick PCB) to a three-dimensional multi-layer redistribution structure. By stacking multiple thin conductive layers with decreasing pitch, the invention achieves both reliable electrical connection and adaptability to highly integrated dies in the vertical dimension.
3Ease of manufacture
If conventional PCB materials are used, then ease of manufacture is maintained, but thermal expansion mismatch causes severe warping due to significant difference between organic and inorganic materials
Solution Approach 1:
The patent applies homogeneity by forming redistribution layers using the same inorganic dummy substrate material that will ultimately support the semiconductor die. This eliminates the organic-inorganic material interface and associated thermal expansion mismatch, preventing warping while maintaining manufacturing simplicity through a unified material system.
Data Source
AI summary
A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically coupling a semiconductor die to the first redistribution layer, and forming a first encapsulant layer on the redistribution layer and around the semiconductor die. The dummy substrate may be removed thereby exposing a second surface of the first redistribution layer. A dummy film may be temporarily affixed to the exposed second surface of the redistribution layer and a second encapsulant layer may be formed on the exposed top surface of the semiconductor die, a top surface and side edges of the first encapsulant layer, and side edges of the first redistribution layer. The dummy film may be removed to again expose the second surface of the first redistribution layer, and a second redistribution layer may be formed on the first redistribution layer and on the second encapsulant layer.