Thin Semiconductor Packages Using Via-Free Leadframes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device packaging technologies face challenges in producing extremely thin, low-impedance, and low-inductance packages with small form factors, which are prone to physical damage and moisture exposure, and often require complex leadframe designs that increase manufacturing costs.
Innovation Solution
The proposed solution involves a packaged semiconductor device design that includes a semiconductor die with terminals on multiple sides, electrically coupled to leadframe and clip portions, and a molding compound, allowing for thin profiles and reduced package size while eliminating the need for package-level vias and using copper-frame based assemblies for efficient material utilization and manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional packaging technologies are used, then device protection is provided, but package thickness increases and form factor enlarges
Solution Approach 1:
The patent transitions from conventional planar packaging to a three-dimensional stacked architecture where the semiconductor die is vertically positioned above the leadframe. This vertical stacking enables the package thickness to be reduced to less than 0.5mm while maintaining full encapsulation protection through the molding compound that surrounds the die from multiple directions.
Solution Approach 2:
The semiconductor die is nested within the molding compound cavity, which is formed by the leadframe structure. The leadframe serves as both the electrical interconnect and the structural container that defines the molding compound cavity, creating a nested configuration where the die is protected by the compound which is in turn contained by the leadframe.
2Ease of manufacture
If complex leadframe designs with package-level vias are used, then electrical interconnects are achieved, but manufacturing cost increases
Solution Approach 1:
The patent eliminates package-level vias from the leadframe structure entirely. Instead of creating complex through-holes and vias in the leadframe for electrical connections, the design uses direct wire bonds from the die pads to the leadframe contact pads on the package leads, extracting the via formation step from the manufacturing process.
Solution Approach 2:
The electrical interconnection is segmented into two distinct stages: first, wire bonding connects the die pads to the leadframe contact pads during die attachment; second, the leadframe leads provide external connections. This segmentation eliminates the need for complex integrated via structures in the leadframe.
3Length of moving object
If thin package profiles are achieved, then form factor is reduced, but device susceptibility to physical damage and moisture increases
Solution Approach 1:
The patent uses a molding compound that fully encapsulates the semiconductor die in a thin package structure. The molding compound acts as a protective shell that conforms to the compact three-dimensional layout, providing environmental protection against moisture and physical damage while maintaining the reduced thickness profile of less than 0.5mm.
Solution Approach 2:
The die is positioned within a precisely formed cavity in the molding compound before final curing, ensuring the die is surrounded by protective material on all exposed surfaces. This pre-encapsulation approach provides beforehand protection against harmful factors while maintaining the thin overall package thickness.
Data Source
AI summary
In a general aspect, a packaged semiconductor device can include a semiconductor die having at least a first terminal on a first side of the semiconductor die and a second terminal on a second side of the semiconductor die. The device can include a leadframe portion electrically coupled to the first terminal of the semiconductor die and a clip portion electrically coupled to the second terminal of the semiconductor die. The device can include a molding compound. A surface of the leadframe portion and a first surface of the molding compound can define at least a portion of a first surface of the device. A surface of the clip portion and a second surface of the molding compound can define at least a portion of a second surface of the device that is parallel to the first surface of the device.