Thinned IC Embedding Mid-Plane Stress Reduction
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Solution Overview
Problem
Thinned integrated circuits face stress and potential damage due to warpage and thermal expansion mismatches when embedded in printed circuit boards, leading to fragility and failure during handling and thermal cycling.
Innovation Solution
A method and apparatus that position the thinned integrated circuit near the mid-plane of the printed circuit board by attaching additional substrate layers to form a thinned integrated circuit sub-assembly, which is then affixed within a cavity of the PCB, using vias for communication and additional substrate layers to align and stabilize the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the thinned integrated circuit is embedded into the PCB, then the space required in the design is reduced, but the thinned integrated circuit suffers warpage or breakage during heating/cooling cycles
Solution Approach 1:
The patent positions the thinned integrated circuit at the mid-plane of the PCB (a spatial dimension) rather than embedding it at the surface, which reduces stress from thermal expansion mismatch while maintaining space efficiency. This dimensional repositioning resolves the contradiction between compact integration and structural integrity.
Solution Approach 2:
The patent introduces a stress relief layer or compliant substrate as an intermediary between the thinned integrated circuit and the rigid PCB, which absorbs thermal stress and prevents warpage or breakage during heating/cooling cycles, thereby maintaining both compact integration and structural integrity.
2Volume of moving object
If the thinned integrated circuit is embedded into the PCB, then the overall design volume is reduced, but the circuit is subject to stresses from thermal expansion mismatch
Solution Approach 1:
By positioning the thinned integrated circuit at the mid-plane of the PCB rather than at the surface, the patent reduces thermal stress exposure while maintaining compact design volume. The mid-plane location experiences less thermal gradient and expansion stress.
Solution Approach 2:
The patent uses a compliant substrate or stress relief layer as an intermediary that decouples the thermal expansion mismatch between the thinned integrated circuit and the rigid PCB, reducing thermal stress while maintaining compact integration.
3Reliability
If additional substrate layers are attached to form a thinned integrated circuit sub-assembly, then stress and flexure on the circuit are reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent divides the integrated circuit assembly into separate functional layers (substrate layer, circuit layer, protective layer) that can be manufactured independently and then assembled, reducing manufacturing complexity while maintaining operational stability through proper layer configuration.
Solution Approach 2:
The patent performs preliminary attachment of substrate layers to form a stabilized sub-assembly before final PCB integration, which reduces stress and flexure on the thinned circuit while allowing each layer to be optimized and pre-tested separately, simplifying the overall manufacturing process.
Data Source
AI summary
A method for mounting and embedding a thinned integrated circuit within a substrate is provided. In one embodiment, the thinned integrated circuit can receive one or more biasing substrate layers on a first surface of the thinned integrated circuit. When the thinned integrated circuit is embedded within a supporting substrate, such as a printed circuit board, the biasing substrate layers can position the thinned integrated circuit toward a centerline of the printed circuit board. Positioning the thinned integrated circuit toward the centerline can increase the resistance to breakage.