Multi-threaded Processor Thread Map Register Granularity
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Solution Overview
Problem
Multi-threaded processors face challenges in dynamically allocating CPU bandwidth among threads and timely handling of interrupts, particularly when dealing with unequal or changing CPU allocations and interrupt masking across multiple threads.
Innovation Solution
A multi-thread superscalar processor with a thread map register that dynamically allocates CPU cycles to each thread and provides per-thread interrupt handling, allowing for granular control of thread execution and interrupt processing, enabling concurrent processing of multiple protocols like Bluetooth and WLAN.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multi-threaded processor alternates execution cycles between threads with protected CPU bandwidth allocation, then each thread receives a fixed percentage of CPU cycles and threads can execute independently during stalls, but the allocation cannot be dynamically changed or made unequal across threads
Solution Approach 1:
The processor implements dynamic thread allocation by allowing the thread context switch mechanism to be reconfigured at runtime. The thread context switch register can be programmatically updated to change which thread executes in each cycle, enabling unequal and dynamic CPU bandwidth allocation among threads without requiring a fixed hardware configuration.
Solution Approach 2:
The processor divides the CPU into multiple independent thread execution contexts, each with its own program counter and register state. This segmentation allows independent control and dynamic allocation of CPU cycles to different threads through the thread context switch mechanism, resolving the contradiction between fixed allocation and dynamic adaptability.
2Reliability
If interrupts are masked during handling to ensure complete processing, then previous interrupts are handled without interference, but new interrupts arriving during handling are not recognized until completion
Solution Approach 1:
The interrupt handling system is segmented into per-thread interrupt contexts. Each thread has its own interrupt mask and handling state, allowing the processor to selectively enable or disable interrupts for specific threads while maintaining reliability for the active thread. This segmentation enables more granular control over interrupt recognition timing.
Solution Approach 2:
The processor implements feedback mechanisms where the completion status of interrupt handling is monitored. When an interrupt is being handled, the system tracks its completion and can adjust interrupt masking behavior based on this feedback, potentially allowing new interrupts to be recognized sooner while still ensuring reliable handling of the current interrupt.
Data Source
AI summary
A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.