Thread Scheduling Logic for Paused Instruction Streams
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Solution Overview
Problem
Pipelined processors face performance limitations due to differences in execution times of instructions, leading to stalls when slower instructions are not completed in time for subsequent instructions, and existing techniques to mitigate this, such as speculative and out-of-order execution, are complex and resource-intensive, especially in multi-threaded environments.
Innovation Solution
A data processing apparatus with a processor core and a pending completion unit that identifies instructions likely to take longer to execute, allowing the scheduling logic to pause or resume instruction scheduling based on the availability of results, enabling the processor to switch to another thread when necessary, thereby simplifying the operation and maintaining throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple instructions are executed in parallel to increase performance, then execution speed improves, but device complexity and power consumption increase significantly
Solution Approach 1:
The processor is divided into multiple execution units (integer ALU, floating point ALU, load/store unit, branch unit) that can operate independently in parallel. Each execution unit handles specific instruction types, allowing simultaneous execution of multiple instructions from different threads without requiring complex inter-unit coordination logic.
Solution Approach 2:
The patent introduces thread dimensionality to resolve instruction dependencies. Instead of complex in-order execution within a single thread, the processor switches to another thread when a pause instruction is encountered or when dependencies would cause stalls, effectively adding a temporal dimension to instruction execution and maintaining pipeline utilization without increasing intra-thread complexity.
2Reliability
If dependency detection logic is added to prevent stalls, then instruction execution accuracy improves, but device complexity and silicon area increase
Solution Approach 1:
The complex dependency detection and resolution logic is extracted from the core execution pipeline and replaced with a simpler thread switching mechanism. When a dependency stall would occur, the processor extracts the current thread from execution, switches to a different thread, and resumes later, thereby maintaining correctness without embedding complex dependency analysis logic in the execution path.
Solution Approach 2:
The thread scheduler acts as an intermediary between the execution units and the instruction stream. Instead of execution units directly detecting and resolving dependencies through complex logic, the scheduler mediates by selecting appropriate threads to execute based on readiness signals and pause instructions, simplifying the overall control logic while maintaining execution accuracy.
3Productivity
If thread switching is implemented to maintain throughput, then productivity improves, but ease of operation deteriorates due to scheduling complexity
Solution Approach 1:
Threads are prepared in advance with pause instructions inserted at appropriate points in the instruction stream where dependencies would occur. This preliminary structuring of thread code allows the scheduler to simply follow pause instructions and switch threads without requiring complex real-time dependency analysis, greatly simplifying the scheduling operation while maintaining high throughput.
Solution Approach 2:
The thread code itself contains the scheduling information through embedded pause instructions. Rather than requiring the scheduler to externally analyze and determine when to switch threads, the threads self-service by indicating their own readiness and pause points, making the scheduling operation straightforward and reducing the complexity of the scheduler logic.
Data Source
AI summary
Data processing apparatus, data processing methods, a method and a computer program product are disclosed. The data processing apparatus includes a processor core operable to execute sequences of instructions of a plurality of program threads. The processor core has a plurality of pipeline stages, one of which is an instruction schedule stage having scheduling logic operable, in response to a thread pause instruction within a program thread, to prevent scheduling of instructions from that program thread following the thread pause instruction and instead to schedule instructions from another program thread for execution within the plurality of pipeline stages.