Thread Transition Management Using Two-Level Register Sets
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Solution Overview
Problem
Advanced processors face challenges in efficiently managing thread transitions, particularly when the number of threads exceeds the available data register capacity, leading to inefficiencies in operation and resource utilization.
Innovation Solution
The implementation of two data register sets with portions of main memory or cache memory serving as second-level registers allows for seamless data movement between these registers, enabling efficient thread execution without stopping current operations, allowing for mirrored or split data management, and supporting a larger number of threads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of threads exceeds the available data register capacity, then more threads can be supported, but operation efficiency deteriorates due to frequent data movement and stopping operations
Solution Approach 1:
The patent segments the register storage into two distinct levels: first-level registers (fast, limited capacity) and second-level registers (slower, larger capacity using main memory or cache). This segmentation allows the system to support more threads by storing thread data in the second-level registers when first-level registers are full, while maintaining high operation efficiency by keeping actively used thread data in the first-level registers.
Solution Approach 2:
The patent introduces a new dimension of memory hierarchy by adding second-level registers beyond the traditional first-level registers. This dimensional expansion creates a two-tiered register system where thread data can be distributed across both levels, effectively increasing the total register capacity available for thread management without compromising the speed of frequently accessed data.
2Reliability
If data is moved between first-level and second-level registers, then thread execution can continue without stopping, but data movement overhead increases
Solution Approach 1:
The patent implements preliminary action by pre-loading thread data into the first-level registers before it is needed for execution. The thread data structure includes a data portion and a status portion that tracks whether data is present in the first-level registers. This allows the processor to quickly determine if data is already available or needs to be fetched from second-level registers, reducing the overhead of data movement by performing it in advance rather than waiting for execution needs.
Solution Approach 2:
The patent enables self-service through automatic data management mechanisms where the processor autonomously manages data between first-level and second-level registers based on thread execution needs. The status portion of the thread data structure and the register allocation logic work together to automatically determine when data should be moved, eliminating the need for manual intervention or complex control logic, thereby reducing overhead while maintaining execution continuity.
Data Source
AI summary
A system and process for managing thread execution includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the threads. Data for the threads may be moved between the first-level registers and second-level registers for different modes of thread processing.