Three-Gate Flash Memory Cell Array with Individual Bit Control
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Solution Overview
Problem
Existing split gate non-volatile memory cell arrays cannot perform true single bit operation, where each memory cell can be individually programmed, read, and erased without affecting adjacent cells.
Innovation Solution
The reorientation of program-erase gate lines, source lines, and word lines in a 3-gate memory cell array from horizontal to vertical configurations allows for independent programming, reading, and erasing of each memory cell, enabling true single bit operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are arranged in rows and columns with shared source lines, bit lines, select gate lines, and PE gate lines, then the array can be compact and efficient, but individual erasure of each memory cell is not possible (pairs of rows must be erased together)
Solution Approach 1:
The PE gate line is segmented into multiple independent lines, with each PE gate line controlling only one row of memory cells. This segmentation allows individual row erasure operations, enabling true single bit operation where each memory cell can be individually programmed, read, and erased without affecting adjacent cells.
2Device complexity
If PE gate lines are configured horizontally to connect pairs of rows, then the array architecture is simplified, but interference occurs between adjacent memory cells during erasure operations
Solution Approach 1:
The PE gate lines are divided into multiple independent horizontal lines, each serving a single row. This prevents the simultaneous erasure of multiple rows and eliminates interference between adjacent memory cells during erasure operations.
Solution Approach 2:
Instead of having one PE gate line control multiple rows (many-to-one), the invention inverts the relationship so that each row has its own dedicated PE gate line (one-to-one). This inversion of the control relationship enables precise individual cell operation.
3Productivity
If source lines connect all source regions in a column, then column-wide operations are efficient, but individual cell selection and operation become difficult
Solution Approach 1:
By combining segmented PE gate lines (controlling individual rows) with column-wide source lines, the invention achieves local control where needed (row selection via PE gate) while maintaining global connectivity for efficiency (column-wide source sharing). This allows individual cell operation while preserving column operation efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables individual control over each memory cell, preventing interference with adjacent cells during programming, reading, and erasing, thus achieving independent operation of each memory cell in the array.
Implementation Method 1
A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18
Implementation Method 2
electrons on the floating gate 20 to tunnel through the intermediate insulation from the floating gate 20 to the PE gate 30 via Fowler-Nordheim tunneling
Implementation Method 3
Some of the heated electrons will be injected through the gate oxide onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20
Data Source
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AI summary
A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.