Three-Inverter Voltage Level Shifter With Capacitive Spike Control
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Solution Overview
Problem
Conventional voltage level shifters for integrated circuits suffer from hot carrier effects due to large voltage spikes, leading to device degradation and instability, and are complex, making them unsuitable for high-speed applications.
Innovation Solution
A circuit comprising three inverters and capacitors that effectively shifts voltage levels between low and high operating voltages, minimizing voltage spikes and reducing complexity by using PMOS and NMOS transistors with capacitors to manage voltage transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional voltage level shifters are used to interface low voltage ICs with high voltage circuits, then voltage level shifting is achieved, but hot carrier effects occur due to large voltage spikes causing device degradation and instability
Solution Approach 1:
The circuit is divided into three separate inverters (first inverter with PMOS 228 and NMOS 230, second inverter with PMOS 232 and NMOS 234, third inverter with PMOS 240 and NMOS 242) instead of using a single complex level shifter. Each inverter handles a portion of the voltage transition, segmenting the voltage spike problem into smaller, manageable transitions that reduce hot carrier effects in individual devices.
Solution Approach 2:
Capacitors 210 and 212 are introduced as intermediary elements to couple the inverters and manage voltage transitions. These capacitors act as mediators that smooth voltage changes and prevent direct coupling of large voltage spikes between different voltage domains, thereby reducing hot carrier effects while maintaining signal integrity.
2Adaptability or versatility
If conventional voltage level shifters are used, then voltage level shifting is achieved, but the circuit complexity increases requiring additional levelizing circuitry
Solution Approach 1:
The three inverters are configured to perform multiple functions: they provide voltage level shifting between low and high voltage domains, simultaneously act as signal buffers, and the capacitors provide both coupling and voltage transition management. This multi-functionality eliminates the need for separate levelizing circuitry that would otherwise be required.
Solution Approach 2:
The voltage level shifting function is merged with the inverter chain structure. Instead of using a dedicated complex level shifter circuit plus separate levelizing circuitry, the patent combines these functions into a unified three-inverter structure with capacitive coupling, reducing overall circuit complexity while maintaining adaptability for interfacing different voltage levels.
3Productivity
If conventional voltage level shifters are used, then voltage level shifting is achieved, but switching speed is reduced due to circuit complexity
Solution Approach 1:
The capacitive coupling between inverters enables dynamic voltage transition management. The capacitors charge and discharge during switching transitions, actively managing the voltage changes to enable faster switching speeds compared to static complex level shifter circuits. This dynamic approach allows the circuit to adapt to high-speed switching requirements.
Solution Approach 2:
By segmenting the voltage transition across three inverters rather than one complex stage, each inverter operates at reduced stress with smaller voltage swings, enabling faster individual switching. The segmented approach reduces the propagation delay compared to a single complex level shifter stage, improving overall switching speed.
Data Source
AI summary
A circuit, includes first, second, and third inverters. The first inverter has a first input coupled to a first port and a first output coupled to a second port. The second inverter has a second input coupled to the second port and a second output coupled to the first port. The third inverter has a third input coupled to the first port through a first capacitor and to a third port. The third inverter has an output coupled to the second port through a second capacitor. The circuit receives a signal having a voltage between a first voltage potential and a second voltage potential and in response outputs a signal having a voltage between the second voltage potential and a third voltage potential. The third voltage potential is higher than the first and second voltage potentials with respect to ground.