Three-Pin Enhanced Serial Peripheral Interface With Target Feedback
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Solution Overview
Problem
Existing serial bus protocols like I2C, SMBUS, SPI, I3C, and SPMI fail to meet the bandwidth and functionality needs of certain systems while adding unnecessary complexity, and existing solutions like I3C and SPMI require more pins than necessary.
Innovation Solution
The Enhanced Serial Peripheral Interface (ESPI) uses a 3-pin configuration with robust framing mechanisms, embedded interrupts, and target feedback to provide medium bandwidth, flexible byte width, and low pin count, optimizing performance and simplifying design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If I3C or SPMI protocols are used to provide higher bandwidth and more features, then bandwidth and functionality are improved, but device complexity and pin count increase
Solution Approach 1:
The patent extracts only the essential features needed for medium bandwidth communication from complex protocols like I3C and SPMI. It removes unnecessary complexity while retaining core functionality, creating a simplified protocol that achieves comparable bandwidth performance with fewer pins and lower design complexity.
Solution Approach 2:
The patent changes key protocol parameters to optimize for medium bandwidth applications. It uses a 3-pin configuration with specific signal assignments (SDA0, SDA1, SCL), implements flexible byte width (8-32 bytes), and introduces target feedback mechanisms that differ from standard SPI to achieve better bandwidth utilization without requiring the full complexity of I3C or SPMI.
2Productivity
If I3C or SPMI protocols are used to provide higher bandwidth, then bandwidth is improved, but pin count increases
Solution Approach 1:
The patent makes each pin multi-functional to achieve medium bandwidth with only 3 pins. The SDA0 line carries both data and address information, SDA1 carries target feedback and interrupt information, and SCL provides clocking. This multi-functionality allows the protocol to achieve I3C-like bandwidth performance without requiring the 4+ pins that I3C and SPMI require.
3Ease of operation
If SPI protocol is used to provide simple operation, then ease of operation is improved, but bandwidth and functionality are insufficient
Solution Approach 1:
The patent introduces target feedback mechanisms where the target device sends acknowledge/not acknowledge bits and interrupt information back to the initiator during the same bus cycle. This feedback capability, achieved through the bidirectional SDA1 line, enables bandwidth optimization and flow control while maintaining protocol simplicity comparable to SPI, avoiding the complexity of I3C's master-arbitrated architecture.
4Device complexity
If older protocols like I2C or SMBUS are used, then device complexity is reduced, but bandwidth is insufficient
Solution Approach 1:
The patent introduces dynamic elements to the simple I2C/SMBUS foundation. It implements flexible byte width (8-32 bytes per transfer), dynamic bus turnaround sequences, and target feedback mechanisms that adapt to data availability. These dynamic features enable medium bandwidth performance comparable to I3C while maintaining the low complexity and 3-pin configuration of older protocols.
Data Source
AI summary
A bus system, including a clock line, a first data line, and a second data line. The bus system further includes an initiator connected to a first end of the clock line, the first data line, and the second data line. The initiator sends a start indication on the clock line and the first data line, sends command bits followed by address bits on the first data line, and sends a stop indication on the clock line and the first data line. The bus system also includes a target connected to a second end of the clock line, the first data line, and the second data line. The target sends target acknowledge information followed by target interrupt information on the second line while the command bits and address bits are sent.