Three-Terminal Capacitor Interposer Mounting for High-Frequency Noise Reduction
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Solution Overview
Problem
Existing semiconductor devices with discrete components on interposers fail to adequately reduce high-frequency noise between semiconductor chips and decoupling capacitors, leading to insufficient noise reduction effects.
Innovation Solution
A new connection structure between semiconductor chips and wiring substrates, incorporating three-terminal capacitors with specific land and electrode configurations, and thermal expansion coefficient matching to minimize thermal stress and enhance noise reduction, while optimizing solder bump volumes and placement for efficient noise path reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a decoupling capacitor is installed only on the rear surface of the interposer, then the structure is simple, but the high-frequency noise reduction effect is insufficient
Solution Approach 1:
The decoupling capacitor function is segmented into two parts: a first decoupling capacitor installed on the rear surface of the interposer and a second decoupling capacitor installed on the front surface of the interposer. This segmentation allows each capacitor to handle different aspects of noise reduction, with the front surface capacitor providing additional high-frequency noise suppression that the rear surface capacitor alone cannot achieve.
Solution Approach 2:
The capacitor arrangement transitions from a single-plane (rear surface only) configuration to a multi-plane configuration by adding a second decoupling capacitor on the front surface of the interposer. This dimensional expansion creates multiple noise reduction pathways, effectively suppressing high-frequency noise through redundant decoupling paths.
2Ease of operation
If the connection path between semiconductor chip and decoupling capacitor is long, then the layout is flexible, but the inductance increases and noise reduction effectiveness decreases
Solution Approach 1:
The connection path is segmented into multiple short segments by placing the second decoupling capacitor on the front surface near the semiconductor chip. This creates separate, short connection paths from the chip to each capacitor, minimizing the total inductance while maintaining layout flexibility through the interposer's wiring structure.
Solution Approach 2:
The interposer acts as an intermediary structure that provides optimized wiring paths between the semiconductor chip and both decoupling capacitors. The interposer's internal wiring and through-holes create low-inductance connection paths that would be difficult to achieve with direct surface mounting, effectively mediating between layout requirements and electrical performance.
3Ease of manufacture
If solder bump volumes are not optimized, then the manufacturing process is simple, but thermal stress causes cracks in the three-terminal capacitor
Solution Approach 1:
The solder bump volumes are optimized to specific ranges that balance mechanical compliance and thermal stress distribution. By controlling the volume parameters of the solder bumps connecting the three-terminal capacitor to the PCB, the design achieves adequate stress absorption during thermal cycling while maintaining reliable electrical connections, preventing crack formation.
Solution Approach 2:
The solder bumps are designed with optimized volumes that provide beforehand cushioning against thermal stress. The increased solder volume acts as a compliance element that absorbs thermal expansion differences between the capacitor, interposer, and PCB during temperature cycling, preventing stress concentration and crack initiation at the solder joints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces high-frequency noise by creating shorter current paths and minimizing inductance, thereby enhancing noise reduction and preventing thermal stress-induced cracks in the three-terminal capacitors.
Implementation Method 1
the first ground-side land of the first wiring substrate and the first ground-side outer electrode of the three-terminal capacitor are connected to each other with a solder bump interposed between them
Implementation Method 2
thermal expansion coefficient matching to minimize thermal stress and enhance noise reduction
Data Source
AI summary
In an electronic component, a first ground land and a first hot land are provided on a mounting surface of a first substrate. A semiconductor chip is mounted on a first surface and a first ground land and a first hot land are provided on a second surface of a second substrate, and the second surface faces the mounting surface of the first substrate. A three-terminal capacitor is between the first substrate and second substrates. The first ground land of the first substrate and a first ground electrode of the three-terminal capacitor are connected to each other with a solder bump interposed therebetween, the first hot land of the first substrate and a first hot electrode of the three-terminal capacitor are connected to each other with a solder bump interposed therebetween, the first ground land of the second substrate and a second ground electrode of the three-terminal capacitor are connected to each other with a solder bump interposed therebetween, and the first hot land of the second substrate and a second hot electrode of the three-terminal capacitor are connected to each other with a solder bump interposed therebetween.