Three-Terminal Memory Circuit for Simultaneous Writes and Disturb Control
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Solution Overview
Problem
Existing memory circuits face inefficiencies in writing data to multiple cells in a single column simultaneously, leading to increased write times and potential write disturb events.
Innovation Solution
A memory circuit design that allows simultaneous writing to multiple cells in a single column by controlling voltage combinations to avoid unpredictable states, using a three-terminal memory cell structure with ferroelectric material, and employing a word line driver, select line, and bit line configuration to manage voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data are written to multiple cells in a single column simultaneously, then write bandwidth is increased and write times are reduced, but write disturb events may be exacerbated
Solution Approach 1:
The memory cells in a column are divided into two subsets (first subset and second subset) that are programmed independently during the same write operation. This segmentation allows simultaneous programming of multiple cells while maintaining control over voltage application to prevent write disturb events in non-selected cells.
Solution Approach 2:
Different voltage levels are applied to different subsets of memory cells based on their selection status. Fully selected cells receive programming voltages, partially selected cells receive intermediate voltages, and non-selected cells receive reference voltages. This local differentiation of voltage quality enables simultaneous multi-cell programming without causing write disturb events.
2Reliability
If traditional memory write operations are used, then write disturb events are avoided, but write times are increased and write bandwidth is reduced
Solution Approach 1:
The write operation continuously programs multiple subsets of memory cells in the same column during the same time period by maintaining simultaneous voltage application to multiple cell groups. This continuous parallel operation eliminates idle time between sequential writes and maximizes write bandwidth while maintaining reliability through controlled voltage levels.
3Reliability
If voltage combinations are controlled to avoid unpredictable states, then data integrity is maintained, but control circuit complexity is increased
Solution Approach 1:
The control circuit dynamically adjusts voltage levels applied to select lines and bit lines based on the specific write operation requirements. Different voltage combinations are applied depending on which cells are fully selected versus partially selected, enabling flexible control of multiple cell subsets while maintaining data integrity through adaptive voltage management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances write bandwidth and reduces overall write times without exacerbating write disturb events, improving efficiency in data storage operations.
Implementation Method 1
the dielectric layer includes a ferroelectric material and the device is referred to as a ferroelectric random-access memory (FRAM or FeRAM) cell
Data Source
AI summary
A method of writing data to a memory array of three-terminal memory cells includes simultaneously programming a first subset of memory cells in a first column of the memory array to a first logic level by activating a first select line of the first column and a first bit line of the first column, and simultaneously programming a second subset of memory cells in the first column to the first logic level by activating the first select line and a second bit line of the first column.