Through-Dielectric Via Interconnects for Low-RC Multi-Die Packaging
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Solution Overview
Problem
Existing integrated circuit packages face challenges with increasing complexity, requiring multiple device dies with different technologies and functions, leading to increased manufacturing costs and performance optimization issues due to RC delay and voltage drop from through-silicon vias.
Innovation Solution
The formation of through-dielectric vias that penetrate through gap-filling regions to directly interconnect device dies, reducing the need for through-substrate vias and metal lines, thereby minimizing RC delay and voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-substrate vias are used for electrical connection between device dies, then device dies can be connected in stacked packages, but RC delay and voltage drop increase due to connections through multiple layers of metal lines and vias
Solution Approach 1:
The patent transitions from planar metal line connections to vertical through-dielectric via connections, changing the dimensional approach to electrical interconnection. By forming vias that penetrate through dielectric layers directly between device dies, the patent creates a three-dimensional connection architecture that reduces the number of sequential connection layers, thereby reducing RC delay and voltage drop while maintaining connection reliability
Solution Approach 2:
The patent extracts the connection path from the traditional through-substrate via approach that requires multiple metal layers and via layers, and creates a direct through-dielectric via connection. This extraction eliminates unnecessary intermediate connection layers, reducing the overall resistance and capacitance of the electrical path between device dies
2Productivity
If multiple device dies are stacked in the same package to achieve more functions, then manufacturing cost is saved and device performance is optimized, but package complexity increases
Solution Approach 1:
The patent segments the package structure into distinct functional layers including device dies, dielectric layers, and through-dielectric vias. This segmentation allows each component to be optimized independently while maintaining overall system functionality, making the complex multi-die package more manageable and manufacturable through standardized processing steps
Solution Approach 2:
The through-dielectric via structure serves multiple functions: providing electrical connection between device dies, reducing RC delay, and enabling direct vertical interconnection. This multi-functional approach simplifies the overall package design by consolidating connection functions into a single structural element rather than requiring separate connection mechanisms
Data Source
AI summary
A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.