Through-Electrode Chip Layout for Stacked Power Delivery
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Solution Overview
Problem
Semiconductor chips require efficient power distribution and stable electrical connections in a compact, stacked configuration to meet the demands of high-volume data processing in small electronic products.
Innovation Solution
The semiconductor chip design includes through electrodes with protrusions, a power pattern, and interlayer insulating layers, along with rear and front connection electrodes, allowing for efficient power supply and stable electrical connections through hybrid bonding, minimizing space and reducing signal transmission delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through electrodes with protrusions are used to penetrate the body portion, then electrical connection reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The through electrodes are formed with protrusions that extend beyond the rear surface of the body portion before packaging. This preliminary formation of protrusions enables subsequent hybrid bonding with the next stacked chip without requiring additional processing steps, thereby improving electrical connection reliability while avoiding increased manufacturing complexity.
Solution Approach 2:
The protrusions on the through electrodes serve as intermediary bonding structures that facilitate hybrid bonding between stacked semiconductor chips. These protrusions act as mediators that enable reliable electrical connections while simplifying the overall manufacturing process by integrating the bonding interface into the electrode structure itself.
2Reliability
If the power pattern is spaced apart from the through electrodes, then signal interference is reduced, but space utilization decreases
Solution Approach 1:
The power pattern is positioned at specific locations on the rear surface, spaced apart from the through electrodes, creating different functional zones. This local differentiation ensures that power distribution areas are separated from signal transmission areas, reducing electromagnetic interference while optimizing space utilization through strategic placement.
3Productivity
If multiple semiconductor chips are stacked vertically, then data processing volume is improved, but heat dissipation becomes more difficult
Solution Approach 1:
The patent transitions from planar chip arrangement to vertical stacking, utilizing the third dimension to increase data processing capacity. The through electrodes with protrusions enable this vertical integration while the hybrid bonding technique ensures efficient thermal pathways are maintained across stacked chips, addressing heat dissipation challenges in the vertical dimension.
Data Source
AI summary
A semiconductor chip according to an embodiment includes a body portion with a front surface and a rear surface, the body portion being oriented in such a way that the rear surface is above the front surface, first and second through electrodes penetrating the body portion with protrusions that protrude above the rear surface of the body portion, a wiring portion formed under the front surface of the body portion, a power pattern formed over the rear surface of the body portion and spaced apart from the protrusions, an interlayer insulating layer filling spaces between the power pattern and the protrusions, and first and second rear connection electrodes formed over the interlayer insulating layer and respectively connected to the first and second through electrodes, wherein the first rear connection electrode is simultaneously connected to the first through electrode and a part of the power pattern that is adjacent to the first through electrode.