Through Electrode Etch Stop Structure for Precise TSV Contacting
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to achieve reliable structural connections between thin and small-sized through electrode structures and contact wiring patterns, which requires precise etching and process adjustments to ensure structural reliability and prevent physical damage during the fabrication of nanoscale components.
Innovation Solution
The implementation of an etch stop structure with multiple etch stop layers, alternately stacked with different etch selectivities, is used to finely control the etching process, ensuring precise formation of through electrode structures and contact wiring patterns, thereby enhancing the structural reliability between these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the sizes of through electrode structure and wiring pattern are reduced to nanometer scale to achieve thin and light semiconductor package, then the storage capacity and package thickness are improved, but the structural reliability and fabrication precision requirements worsen
Solution Approach 1:
The patent divides the etching process into multiple stages using a multi-layer etch stop structure (first etch stop layer, second etch stop layer, third etch stop layer) with different etch selectivities. Each layer serves as a stopping point for specific etching processes, enabling precise control over the depth and extent of etching at the nanometer scale. This segmentation of the etching process into controlled stages directly addresses the manufacturing precision challenge while maintaining thin package dimensions.
Solution Approach 2:
The patent utilizes parameter changes in the form of different etch selectivities among multiple etch stop layers. Each etch stop layer is designed with specific material properties and etch resistance characteristics that allow selective stopping of etching processes. By changing the parameters of etch stop layers (material composition, thickness, etch resistance), the patent achieves precise control over through electrode structure formation and wiring pattern fabrication at nanometer dimensions.
2Manufacturing precision
If multiple etch stop layers are introduced to control etching precision, then the manufacturing precision is improved, but the device complexity increases
Solution Approach 1:
The etch stop structure with multiple layers serves multiple functions simultaneously: it acts as an etching stop for different etching processes, provides structural support during fabrication, defines precise boundaries for through electrode structures and wiring patterns, and enables sequential processing steps. This multi-functionality reduces the need for separate structures for each function, thereby managing device complexity while achieving high manufacturing precision.
Solution Approach 2:
The patent employs a nested structure where the first etch stop layer, second etch stop layer, and third etch stop layer are sequentially arranged with the through electrode structure passing through them. The etch stop layers are nested within the insulating layers, creating a compact hierarchical structure. This nesting approach allows multiple functional layers to be integrated in a space-efficient manner, managing structural complexity while maintaining precise etching control.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one etch stop layer of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one etch stop layer of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.