3D IC Package Through-Mold Interconnects Bypass Bottom Die
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Solution Overview
Problem
Conventional semiconductor packages face limitations in accommodating stacked die due to size constraints and structural issues, particularly with C4 solder ball connections and wire-bonding approaches, which hinder the integration of complex circuitry and high-density packaging.
Innovation Solution
The development of 3D integrated circuit packages with through-mold first level interconnects, where a top semiconductor die with a larger surface area is conductively coupled to a substrate, bypassing a bottom die, using copper bumps embedded in a molding compound, eliminating the need for through silicon vias (TSVs) and enabling face-to-face stacking without wire-bonds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If C4 solder ball connections are used for flip chip interconnections, then electrical connection between die and substrate is achieved, but the mounting area size limits the ability to accommodate stacked die
Solution Approach 1:
The patent transitions from planar 2D mounting to 3D vertical stacking by implementing through-mold interconnects that extend vertically through the mold compound. This allows multiple die to be stacked in the vertical dimension rather than requiring additional horizontal mounting area, effectively resolving the contradiction between accommodating stacked die and limited mounting area.
2Productivity
If conventional wire-bonding approaches are used, then electrical connection is achieved, but the number of semiconductor die that can be included in a single package is limited
Solution Approach 1:
The patent extracts and eliminates the wire-bonding step entirely by implementing direct through-mold interconnects. The interconnect structure is formed directly within the mold compound during molding, removing the need for subsequent wire-bonding processes. This increases productivity by enabling more die per package while reducing structural complexity by eliminating the wire-bonding infrastructure.
3Adaptability or versatility
If through silicon vias (TSVs) are used for vertical interconnects, then 3D stacking is enabled, but manufacturing complexity and cost increase
Solution Approach 1:
The patent introduces the mold compound as an intermediary medium that contains the vertical interconnects. Instead of forming TSVs through the die itself (which is complex and costly), the interconnects are formed within the mold compound that encapsulates the die. This intermediary approach enables 3D stacking capability while significantly reducing manufacturing complexity and cost, as the interconnects are formed during the standard molding process rather than requiring specialized TSV fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for compact, high-density 3D packaging with improved assembly and structural protection, enabling efficient power delivery and communication between dies, while reducing costs associated with TSVs and accommodating larger circuit densities.
Implementation Method 1
The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die
Implementation Method 2
the solder bumps are heated above their melting point until they reflow and form a connection with the Cu stud bumps of the die
Data Source
AI summary
3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.